NMOS vs PMOS: Differences & When to Use Each

Quick answer

Use an N-channel enhancement MOSFET (NMOS) for most low-side switches, where the transistor controls the load's connection to ground. NMOS usually provides lower on-resistance for a given size and cost, and its ground-referenced source is easy to drive. Use a P-channel enhancement MOSFET (PMOS) when a simple switch is needed between the positive supply and a modest-voltage load, provided its additional loss is acceptable. For efficient high-side switching, especially at higher current or voltage, use an NMOS with a floating high-side driver or charge pump. Select from guaranteed RDS(on) at the actual gate-to-source voltage, rather than relying on VGS(th).

MOSFETs (metal-oxide-semiconductor field-effect transistors) are commonly used to control power delivery to LEDs, motors, sensors, and other electronic loads. An enhancement-mode MOSFET is normally off when no gate-to-source voltage is applied. Applying the appropriate voltage to the gate creates a conductive path between the drain and source terminals.

The main distinction between NMOS and PMOS is the gate voltage required to turn each device on. NMOS requires a positive gate-to-source voltage, and PMOS requires a negative voltage. The difference affects where each transistor is placed in a circuit and how its gate must be driven. For additional background on device operation and terminal functions, see Flux's MOSFET basics guide.

NMOS vs PMOS comparison

Table 1. NMOS and PMOS switching characteristics and design considerations

In schematic symbols, a broken channel line commonly denotes enhancement mode. By comparison, a solid channel often denotes depletion mode, in which the transistor can conduct without an applied gate voltage. Symbol styles vary, so verify the gate (G), drain (D), source (S), body diode, and package pin mapping against the manufacturer drawing.

For a comparison of transistor symbols, see Flux's MOSFET & Transistor Symbols: NMOS, PMOS, NPN, PNP.

Choose NMOS if

An NMOS is commonly used for low-side switching, meaning the transistor is placed between the load and ground. The source can then stay near ground potential, so a microcontroller can control the gate without generating a voltage above the load's supply.

• You are switching a GPIO-controlled LED strip, solenoid, fan, or motor on the low side, and the system can tolerate disconnecting the load's negative terminal from ground.
• You need pulse-width modulation (PWM) efficiency or low conduction loss. Keep the source return close to the driver reference and verify switching loss as well as RDS(on).
• You are switching a higher-voltage load, such as one supplied by a 24 V industrial rail. Choose a device with sufficient voltage margin for transients, a gate driver if required, appropriate transient-voltage-suppression (TVS) protection, and a thermal and safe-operating-area calculation. For example, a MOSFET rated for 30 V may have insufficient voltage margin on a nominal 24 V supply if switching transients exceed the rating.
• You need an efficient high-side path and can add a floating driver, charge pump, or isolated supply.
• Package area, heat, or current makes a PMOS solution unattractive. For example, a high-current switch may require a larger PMOS package to dissipate the additional heat caused by higher RDS(on).

Choose PMOS if

A PMOS is commonly used for high-side switching, where the transistor is placed between the positive power supply and the load. The arrangement allows the load's ground connection to stay intact when power is disconnected.

• You need a simple high-side switch for a low-voltage sensor rail and modest current, without interrupting the sensor's ground connection.
• The load must stay ground-referenced while the positive rail is disconnected.
• A 3.3 V controller shares the PMOS source rail, can pull the gate to the same rail for off, and can pull the gate low enough for the required negative VGS. Check power sequencing and absolute maximum VGS.
• You need a simple reverse-battery stage and accept PMOS conduction loss. In a reverse-battery protection circuit, connect drain to raw battery input and source to protected output so the body diode initially conducts from drain to source under correct polarity. Gate bias then turns on the channel.
• Simplicity matters more than achieving the lowest RDS(on), and the thermal result is acceptable.

A PMOS with its source above the MCU supply cannot be driven safely by a 3.3 V GPIO alone. A GPIO high may not make VGS zero, and an unpowered MCU can be back-powered through its pins. Use a level shifter and, on larger supply rails, a gate-to-source clamp selected for the MOSFET's VGS limit.

Real parts found in the Flux library

The following parts are selection examples rather than universal load-current recommendations. Absolute drain-current (ID) ratings depend on case or ambient conditions and do not replace PCB copper, thermal, pulse, and safe operating area (SOA) checks. SOA specifies the combinations of voltage, current, and operating duration under which a transistor can operate without exceeding its electrical or thermal limits.

• AO3400A, N-channel, SOT-23. The Alpha & Omega Semiconductor datasheet, Rev. 3, December 2011, specifies 30 V VDS and ±12 V VGS. Maximum RDS(on) is 48 mΩ at VGS = 2.5 V, ID = 3 A, making its on-resistance specification relevant to 3.3 V GPIO drive.
• DMP2035U-7, P-channel, SOT-23. The Diodes Incorporated datasheet, DS31830 Rev. 4-2, October 2013, specifies −20 V VDSS and ±8 V VGSS. Maximum RDS(on) is 45 mΩ at VGS = −2.5 V, ID = −4 A, and 62 mΩ at VGS = −1.8 V, ID = −2 A. The specifications refer to the cited 2013 revision; check the current manufacturer datasheet before final component selection.
• IRLML0060TRPBF, N-channel, Micro3/SOT-23. The Infineon datasheet, revision-history date 2016-12-20, specifies 60 V VDS and ±16 V VGS. Maximum RDS(on) is 116 mΩ at VGS = 4.5 V, ID = 2.2 A, TJ = 25°C, or 92 mΩ at 10 V, 2.7 A. The part is a useful 60 V-class example for a 24 V load, but its guaranteed on-resistance is not specified at 3.3 V. Use an appropriate driver rather than assuming full enhancement from a GPIO.

Design considerations

Power, protection, and decoupling

A MOSFET gate behaves like a capacitor, so the driver must briefly supply current to charge the gate during turn-on and remove the charge during turn-off. Place the driver's local bypass capacitor close to its supply and return pins, keep the gate loop small, and include a gate-to-source pull resistor so startup and reset states are defined. A series gate resistor can control ringing and switching speed, although slower switching increases power loss.

For an inductive low-side load, the GPIO drives only the MOSFET gate and must not supply motor or coil current. Place a flyback diode with its anode at the switched drain and cathode at the positive supply. The diode gives the inductive current a path when the MOSFET turns off.

Select the diode's reverse-voltage, current, surge, and recovery characteristics for the load and PWM strategy. A simple flyback diode produces slow current decay and may not suit applications requiring fast actuator release.

Check repetitive switching energy, avalanche expectations, junction temperature, transient thermal impedance, and SOA. During a slow voltage ramp, such as charging a capacitive load, the MOSFET may spend time in its linear operating region. The resulting inrush current and power dissipation may exceed its linear SOA even when the final steady-state current is acceptable.

Clock, crystal, programming, and debug

A discrete MOSFET switch needs no clock, crystal, firmware toolchain, or programming header. However, the microcontroller or other circuit controlling the gate can affect switching behavior during startup and shutdown. GPIOs can float, default to inputs, pulse during boot, or conduct through protection diodes when unpowered.

Add hardware pull-up or pull-down resistors at the gate to establish a safe default state, and verify reset, bootloader, brownout, and power-domain sequencing.

Layout and RF/EMI

Switching currents change rapidly when a MOSFET turns on or off. The current path through the supply, load, MOSFET, and return therefore forms a high di/dt loop, where di/dt describes the rate of current change over time. Keep the loop compact to limit unwanted voltage spikes and electromagnetic interference.

Place the flyback diode or clamp physically near the inductive current loop. Use adequate copper and vias for heat and current, but check the datasheet's mounting conditions before relying on the headline ID rating. Flux's guide to via stitching explains how vias can connect copper planes and affect return-current paths, EMI, and thermal behavior.

Rapid voltage changes at the MOSFET drain during switching can couple through gate-drain capacitance and radiate from load wiring. Adjust gate resistance, provide a low-inductance source return to the driver, and separate noisy switching nodes from crystals, antennas, analog inputs, and high-impedance sensor traces.

For radio-frequency (RF) applications, general switching MOSFET models and breadboard wiring are usually inadequate. Use manufacturer RF models or scattering parameters (S-parameters), which describe how high-frequency signals behave at a device's terminals, when applicable.

High-side NMOS, load switches, and reverse blocking

A high-side NMOS gate must be driven above its source voltage. One method is a bootstrap driver, which uses a capacitor to provide the elevated gate voltage needed when the source approaches the positive supply rail.

Bootstrap drivers are compact for switching converters, but their capacitors generally need periodic recharging. The required refresh can limit duty cycle and maximum on-time. A bootstrap-only driver may therefore be unsuitable for a high-side switch that must stay on continuously, such as a permanently powered load. For continuous operation, use a charge-pump driver, isolated bias supply, or driver specifically rated for continuous high-side operation.

An integrated load switch combines a switching transistor with control circuitry in one IC. Depending on the device, the circuit can provide controlled voltage rise time, current limiting, thermal shutdown, and optional output discharge.

When selecting a load switch, check reverse-current behavior in both enabled and disabled states. Output discharge may interfere with another powered rail or cause unwanted current paths. Sensor signal pins may also power a disconnected sensor through their input/output protection structures, so the entire circuit must be considered.

Some applications require a disconnected power path to block current in either direction, including current that might flow backward from a powered output. For such bidirectional off-state blocking, use back-to-back MOSFETs or a load switch/eFuse specified for reverse-current blocking. A single MOSFET can conduct channel current in either direction when turned on, but its intrinsic body diode still permits current in one direction when the transistor is off.

Minimal reference circuits

NMOS low-side switch

Assumptions: 3.3 V GPIO; AO3400A used only where its 30 V rating has adequate margin; example component values of 47 Ω for the gate resistor and 100 kΩ for the gate-to-source pull-down.

For a higher-voltage application, such as a 24 V industrial load, substitute a device rated for the expected supply transients. A 60 V-class or higher MOSFET may be appropriate after surge analysis, along with a suitable TVS or clamp.

The IRLML0060TRPBF described in the component examples has an on-resistance specification at VGS = 4.5 V, so use a driver that provides at least the characterized 4.5 V gate condition rather than relying on direct 3.3 V drive.

PMOS high-side switch

Assumptions: Source rail equals the MCU's 3.3 V logic rail; DMP2035U-7; example component values of 100 kΩ for the gate-to-source pull-up and 1 kΩ for the GPIO series resistor. Load current must be established by the project requirements.

The direct GPIO circuit assumes the PMOS source and the MCU logic-high voltage are both 3.3 V. The same connection is not suitable when the PMOS source is at 5 V, 12 V, or 24 V and the GPIO high is only 3.3 V.

For higher supply voltages, use a small transistor or dedicated high-side driver to pull the PMOS gate down, together with a gate-to-source pull-up resistor for turn-off. Add a gate-to-source clamp when the supply voltage or switching transients could exceed the MOSFET's maximum VGSS rating.

FAQ

NMOS vs PMOS: which is better for switching?

What is the PMOS vs NMOS symbol difference?

Can a 3.3 V GPIO drive an NMOS directly?

Can a 3.3 V GPIO drive a PMOS high-side switch?

What is the difference between a high-side and low-side MOSFET switch?

Which MOSFET should switch a GPIO LED strip or motor?

Should I use PMOS for reverse battery protection?

Sources

• Alpha & Omega Semiconductor AO3400A datasheet, Rev. 3, December 2011
• Diodes Incorporated DMP2035U datasheet, DS31830 Rev. 4-2, October 2013
• Diodes Incorporated DMP2035U current manufacturer datasheet
• Infineon IRLML0060 datasheet, revision-history basis dated 2016-12-20
• TI, Avoid Common Mistakes When Selecting and Designing With Power MOSFETs
• Infineon, AN-978 HV Floating MOS-Gate Driver ICs
• TI, Reverse Current Protection in Load Switches
• TI, Achieve Bidirectional Control and Protection Through Back-to-Back Connected eFuses
• TI, Reverse Current/Battery Protection Circuits
• Flux, MOSFET & Transistor Symbols: NMOS, PMOS, NPN, PNP