ESP32-C5 Review
Worked for 11 mins 9 sec
The focused correction reports the Molex replacement has now persisted. I’m re-reading the live schematic and PCB one final time to resolve the earlier stale-state mismatch.
Thought for 1 min 8 sec
The live source-of-truth still shows the old Yuandi connector, so the claimed replacement did not persist. I’m reverting the partial Job 3G1 edge-placement commits to
#4a24e477 rather than leaving an unverified mixed state.Worked for 1 min 7 sec
Job 3G1 — BLOCKED and reverted
The replacement operation reported success, but independent live read-back still showed J3 as the original Yuandi
TF-01A / C2889258. The Molex 5033981892 replacement therefore did not persist reliably.To avoid leaving a mixed state with moved connectors and the old J3 footprint, all 13 partial Job 3G1/placement commits were reverted to checkpoint
#4a24e477.- J3 remains the original Yuandi connector.
- J1/J3 edge-placement changes were removed.
- The premature change-log update was removed.
- No XIAOs, routing, copper, outline, or unrelated circuitry remain changed.
Final status: BLOCKED. The exact Molex component replacement backend must persist successfully before service-edge placement can resume.
Diagnose replacement issue
Create Molex component
Try Hirose alternative
Keep Yuandi temporarily
Review commit diffs
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U3 TPS552882 Completion Checkpoint
Scope and timestamp
- Scope: U3 TPS552882 protected USB input to regulated approximately 5.06 V post-shunt USB_5V, including controlled reduced-power 5 V fallback and 9–20 V PD operation.
- Final scoped ERC/SLC review: 2026-07-23T21:43:09.002Z. Keyword-scoped checks for U3, R27, R28, and U3_EN_UVLO returned zero findings; no unexplained error, warning, open, or uncertain result remains in the changed scope.
- This checkpoint does not claim 5 V / 5 A capability from a 5 V fallback source.
Reference evidence
- Texas Instruments TPS552882 datasheet, Section 7.3.4 “Enable and Programmable UVLO,” Equation 1 and Equation 2; Section 6.5 EN/UVLO electrical characteristics; Section 6.1 absolute maximum ratings.
- Datasheet equations:
VIN_ON = VUVLO × (1 + R27/R28)andVIN_ON − VIN_OFF = IUVLO × R27, thereforeVIN_OFF = VIN_ON − IUVLO × R27. - Datasheet limits used: VUVLO = 1.20 V minimum, 1.23 V typical, 1.26 V maximum; IUVLO = 4.5 µA minimum, 5.0 µA typical, 5.5 µA maximum. R27 and R28 are 1%.
Final EN/UVLO values and thresholds
- R27 (upper, VBUS_PROTECTED to U3_EN_UVLO): 68.1 kΩ ±1%, 0603, 0.1 W.
- R28 (lower, U3_EN_UVLO to GND): 28.2 kΩ ±1%, 0603, 0.1 W.
- Nominal turn-on:
1.23 × (1 + 68.1/28.2) = 4.200 V. - Nominal hysteresis:
5.0 µA × 68.1 kΩ = 0.3405 V. - Nominal turn-off:
4.200 − 0.3405 = 3.860 V. - Worst-case turn-on, including VUVLO limits and both resistor tolerances: 4.040 V minimum to 4.364 V maximum.
- Worst-case turn-off, including VUVLO and IUVLO limits and both resistor tolerances: 3.670 V minimum to 4.055 V maximum.
- Worst-case programmed hysteresis: 0.303 V minimum to 0.378 V maximum.
- This allows startup from a valid ordinary 5 V Type-C source after realistic cable/eFuse loss while providing meaningful hysteresis and removing switching before deep source collapse. Bench verification under worst-case source/cable/load transients remains required.
20 V and resistor stress verification
- At VIN = 20 V, nominal EN divider voltage is approximately 5.857 V before hysteresis-current injection and approximately 5.956 V with nominal 5 µA sourcing current, below the EN absolute maximum of 20 V.
- At VIN = 20 V, nominal dissipation is approximately 2.9 mW in R27 and 1.3 mW in R28, far below each 0.1 W rating; resistor voltage stress is also benign for 0603 parts but must remain covered by the selected resistor MPN rating.
- U3 VIN recommended range is 2.7–36 V. The revised divider therefore preserves 9–20 V PD startup; U3 soft-start remains the datasheet-defined 4 ms internal reference ramp once VIN and EN/UVLO qualify.
Verified fallback path
- Direct schematic inspection shows
VBUS_RAW → U2 TPS259474 → VBUS_PROTECTED → U3 TPS552882 → R19 shunt → USB_5V. - No separate complete 5 V bypass from VBUS_RAW or VBUS_PROTECTED to USB_5V/SYS_5V is present. U3 is the documented 5 V fallback conversion path.
- U3 EN is derived only from protected input presence and UVLO level. It does not authorize downstream load level.
Required source-dependent behavior
- Unknown/default-current or invalid source: essential-load-only or shutdown; never infer 1.5 A or 3 A. Scanner branches disabled, charging disabled, and no repetitive overload/eFuse cycling.
- Valid 5 V / 1.5 A source: cap total source draw conservatively below 1.5 A including conversion loss and housekeeping. Coordinator and essential peripherals only by default; scanner branches off or strictly sequenced within a measured budget; charging off; fan available for safety.
- Valid 5 V / 3 A source: cap total source draw below 3 A including conversion loss. Normal passive scan only if measured budget fits; stage scanner branches; fast charging off, or permit only low-rate charging after measured system headroom is established; fan available for safety.
- Negotiated 9–20 V PD source: revised UVLO preserves U3 startup. Allowed load remains limited by the verified contract, U2 eFuse ceiling, converter thermal/current capability, and downstream policy; it is not authorized by U3 EN alone.
- Scanner branches remain disabled at startup until source capability is known. Fast charging remains disabled at startup and on unknown/default-current or 1.5 A sources.
- U2 eFuse current limiting is the final hardware ceiling, but load-switch and charger controls must prevent repetitive overload/eFuse cycling.
- U4/U9 source isolation must continue to prevent backfeed; their incomplete support networks are intentionally unchanged here.
Deferred control dependencies
- Complete STUSB4500 attach, contract, advertised-current interpretation, and valid-source reporting.
- Complete TPS259474 U2 PG/FLT/status handling and verify its current-limit configuration against connector/cable/source constraints.
- Implement fail-safe downstream load policy in the coordinator and load-switch enables: scanners default off, charger default off, source-profile current caps, staged enabling, measured headroom checks, fault shutdown/retry policy, and fan safety availability.
- Verify U4/U9 source-isolation support networks and backfeed prevention when those blocks are completed.
- Existing status nets such as USB_INPUT_PG are not claimed operational beyond their present schematic connectivity. No fake status signal or cross-block control connection was added in this U3-only pass.
Remaining U3-only validation requirements
- Perform loop-gain measurement or validated power-stage simulation over 5 V fallback and 9–20 V PD inputs, load range, component tolerances, and actual capacitor DC-bias/ESR to confirm stability.
- Select exact capacitor MPNs whose vendor DC-bias curves prove required effective capacitance at operating voltage.
- Bench-check startup/shutdown thresholds, source droop/chatter immunity, load transients, MOSFET/inductor/shunt/IC temperatures, ripple, and EMI for each permitted source profile.
Scope and timestamp
Reference evidence
Final EN/UVLO values and thresholds
20 V and resistor stress verification
Verified fallback path
Required source-dependent behavior
Deferred control dependencies
Remaining U3-only validation requirements
