Job 1F Approval Checkpoint - Revised
Approval status
NOT APPROVED. No schematic implementation is authorized.
The fail/restore control architecture is accepted as the current technical direction, but the scanner isolation timing requirement remains unresolved. This file is a stop-point, not an implementation approval request.
Corrections from the prior checkpoint
- Removed the claim that 5.97 us is a supported or guaranteed passive-fallback time.
- Retired 1.40 us as a qualified active-shutdown value.
- Classified all PFET gate timing based on typical Qg as nominal engineering estimates only.
- Replaced simultaneous
/PRE and /CLR use with a fail-dominant D-flip-flop topology.
- Added comparator overdrive-development time and VBUS collapse-slope dependence.
- Added documented stale STUSB POWER_OK behavior and explicit ATTACH/PG gating.
- Kept 1.838 A and 0.750 A explicitly provisional.
- Selected a guaranteed restore-delay component and timing.
- Added a read-only relevant ERC inventory.
Resolved architecture decisions
Fail-dominant latch
- TI
SN74LVC1G74DCTR.
- D tied high.
/PRE tied permanently high; no active preset path./CLR driven directly by active-low USB fast-good comparator output.- Q is
SCANNER_ALLOW_LATCHED; low is safe.
- Restore uses a delayed rising clock edge.
- A fault concurrent with a clock edge is dominated by asynchronous
/CLR; simultaneous /PRE and /CLR assertion is structurally impossible.
Fast detector
- TI
TLV3201AIDBVR.
- TI
REF3425IDBVR.
- 20.0 kOhm / 10.0 kOhm 0.1% divider.
- Calculated threshold: 7.468-7.532 V, nominal 7.500 V.
- The 55 ns comparator maximum is valid only after the specified overdrive exists.
- A 20 mV comparator overdrive requires approximately 60 mV additional VBUS movement; total timing depends on collapse slope.
Stale POWER_OK prevention
RESTORE_VALID requires all of:
- STUSB ATTACH currently active.
- POWER_OK2 or POWER_OK3 indicating an approved 9 V or 12 V contract.
- U2 PG valid.
- U3 PG valid.
- USB fast-good valid.
Because ATTACH, U2 PG, and fast-good must all be current, stale POWER_OK2/3 assertion after detach cannot cause restoration.
Restore delay
Selected: TI TPS3808G01DBVT.
- VDD: PERIPH_3V3.
- SENSE held valid.
- MR driven by RESTORE_VALID.
- CT open.
- RESET open drain drives the latch clock.
- Guaranteed release delay: 12 ms minimum / 20 ms typical / 28 ms maximum.
- Any invalid condition restarts the timer.
The restore-delay selection is resolved.
Scanner gate-control topology
Per bank:
SN74LVC1G08DCKRG4 generates BANK_COMMAND AND SCANNER_ALLOW_LATCHED.- 1 kOhm series gate resistor drives
2N7002Q-7-F.
- 100 kOhm resistor pulls the 2N7002 gate to ground.
- 2N7002 pulls the high-side PFET gate low to turn the bank on.
- PFET gate-to-source resistor turns the bank off and provides safe default.
- Logic power loss disables the LVC output through Ioff; the 2N7002 turns off; the PFET gate returns to source.
- Pull-up/pull-down contention is current-limited by the PFET gate pull-up resistor.
A provisional 220 Ohm pull-up would draw approximately 23.7 mA and dissipate approximately 124 mW at 5.211 V; a minimum 250 mW resistor would be required. This value is not approved because PFET dynamic timing remains unbounded.
Unresolved active isolation selection
Parts reviewed include:
- CSD25402Q3A.
- DMP2066LDM-7.
- TPS22918.
- TPS22930A.
- TPS22995.
- MIC9416x.
- TPS259474 used as a bank switch.
None provides the required manufacturer-guaranteed normal-disable time below 10 us for this application. The discrete PFETs publish typical-only gate charge, and the integrated switches publish typical-only normal turn-off timing or slower behavior.
Therefore the active isolation selection is not resolved to production-proof level. Per instruction, no implementation approval is requested.
Provisional power arithmetic
- Post-scanner engineering allocation: 1.838 A provisional.
- Battery ceiling: 2.588 A provisional calculated.
- Difference: 0.750 A provisional calculated.
These are not production-qualified until the underlying load and efficiency limits are measured or manufacturer-guaranteed.
Relevant ERC inventory
Read-only snapshot, 2026-07-24T17:47Z:
- U2 PGTH/FLT floating.
- U2 OVLO/OVCSEL floating.
- USB_INPUT_PG is not a completed pulled-up status net.
- U16-U24 VBUS: nine floating-pin errors and nine missing-power errors.
- U13 P00-P04 candidate bank-command pins floating; additional U13 pins also floating.
- U1 POWER_OK2/3 presently no-connect; no current ERC finding.
- U25 E2/H2 network has no ERC finding but remains electrically unsuitable for source-priority qualification.
- Numerous unrelated scanner GPIO, mux, GPS, SD, fan, USB, and passive floating-pin/missing-power findings remain.
No ERC finding was modified, dismissed, or waived.
Exact unblock criteria
Implementation approval requires one of the following:
- A production isolation device with manufacturer-guaranteed disable timing that closes the complete detector + latch + logic + gate/isolation path below 10 us over voltage and temperature; or
- Explicit approval of a characterization-based requirement, with worst-case sample testing, hot/cold/voltage coverage, production test limits, guard band, and failure handling for the selected discrete PFET topology.
Additionally required:
- Bound or measure VBUS collapse slope and U3 transient behavior.
- Verify STUSB POWER_OK2/3 NVM programming, stale-state behavior, ATTACH gating, and reset/re-attach operation.
- Qualify the provisional post-shutdown load and battery ceiling.
Recommendation
Do not modify the schematic yet. Retain this fail-dominant architecture and continue with a focused scanner-isolation qualification job. Job 1F remains blocked and STOP-SHIP remains active.