Job 3G1 Correction
there are two pads "IN_5" and "GND_4" which look like they should simply be GND
Thought for 11 sec
Those pads indicate the TPS259830ONRGER, not the LTC4373. They must not both be GND:
IN_5/ Thermal Pad 1 → INGND_4/ Thermal Pad 2 → GND
TI specifies two electrically distinct exposed pads; shorting both to GND would directly short the input rail. The footprint naming may be awkward, but that separation is electrically required.
can you tell me what the reference designator is for the TPS259830ONRGER part/
Thought for 25 sec
The TPS259830ONRGER reference designator is IC1.
Inspect IC1 footprint
Check IC1 nets
Validate power path
Report IC1 issues
Here's an image of the pads, "IN_5" connects to "power"
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STUSB4500 Completion Checkpoint
Scope and completion time
Focused U1 STUSB4500QTR USB-C PD sink block completed and directly inspected. Focused ERC/SLC evidence timestamp: 2026-07-23T22:33:03.048Z. U3 and U10 were preserved. The only U2 change was removal of raw-VBUS EN and replacement with the fail-safe STUSB-controlled EN interface.
Final production parts
- U1: STUSB4500QTR, STMicroelectronics, QFN-24 + exposed pad.
- C29, C30, C60: TDK C1608X7R1V105K080AC, 1 uF ±10%, 35 V, X7R, 0603. C29=VREG_1V2, C30=VREG_2V7, C60=VDD/VBUS_RAW.
- R36: Vishay CRCW2512499RFKEGHP, 499 ohm ±1%, 1.5 W pulse-withstanding 2512. VBUS_RAW to VBUS_VS_DISCH; 40.1 mA at 20 V, below the ST 50 mA limit.
- R37: Stackpole RNCP1206FTD1K00, 1 kohm ±1%, 0.5 W, 1206. VBUS_PROTECTED to DISCH; 20 mA and 0.4 W transient at 20 V.
- R38: Yageo RC0603FR-0710KL, 10 kohm ±1%, 0603 RESET pull-down.
- R39/R40: Yageo RC0603FR-074K7L, 4.7 kohm ±1%, 0603, the single root-bus SCL/SDA pull-up pair to PERIPH_3V3. Assumption: compact board, seven root devices, 400 kHz target; rise time must be measured and value revised only if measured bus capacitance requires it.
- R41-R45: Yageo AC0603FR-07100KL, 100 kohm ±1%, 0.1 W, 75 V, 0603. R41 base-current limiter, R42 Q4 base-emitter off bias, R43 U2 EN pull-down, R44 ATTACH pull-up, R45 ALERT pull-up.
- Q4: Diodes Incorporated BC807-25-7-F, PNP, 45 V VCEO, SOT-23. Inverts U1 active-low VBUS_EN_SNK into U2 active-high EN.
Connectivity and safe-state behavior
- J1 CC1/CC2 connect directly to U1 CC1/CC2. CC1DB/CC2DB connect to the corresponding CC nets for dead-battery Rd operation. No external 5.1 kohm Rd was added.
- VDD is on receptacle-side VBUS_RAW with C60. VSYS is grounded because no independent always-on system supply exists. Both U1 grounds and exposed pad are GND.
- VREG_1V2 and VREG_2V7 each have an exact 1 uF production MLCC.
- ADDR1=ADDR0=0, selecting 7-bit I2C address 0x28. SCL/SDA are on I2C_ROOT_SCL/SDA.
- RESET is active high and held safely released by R38 to GND. Firmware may reset through register/system power cycling; no coordinator reset GPIO was consumed.
- U1 VBUS_VS_DISCH senses receptacle-side VBUS through R36. DISCH reaches protected-side VBUS through R37. Both paths are current/power rated for 20 V transient discharge and do not connect downstream power back to VDD.
- U1 VBUS_EN_SNK low sinks through R41, turning on Q4 and raising U2 EN from VBUS_RAW. R42 holds Q4 off and R43 holds U2 EN low when U1 is unpowered, reset, detached, or not authorizing the sink path. A valid ordinary attached 5 V source may enable U2; no high-voltage contract is required.
- ATTACH_N and ALERT_N are pulled to PERIPH_3V3 and routed to coordinator X1 D0/GPIO1 and D1/GPIO0. POWER_OK2, POWER_OK3, GPIO, A_B_SIDE and NC are intentionally marked no-connect; contract details are read over I2C. Orientation is handled internally by independent CC1/CC2 inputs; no SuperSpeed mux is present.
- No cable, detach, reset, failed negotiation, invalid source, or power removal leaves Q4 off and U2 EN pulled low. Downstream scanner/charger authorization remains a later firmware/load-switch policy and is never implied by U2 being enabled.
PD sink PDO/NVM policy
Program and verify STUSB4500 NVM with fixed sink PDOs in the order required by ST's highest-voltage/highest-power selection algorithm:
- PDO1 mandatory fallback: 5 V. Current request/advertisement must follow valid Type-C Rp or negotiated source capability; firmware must never assume 3 A from default current and must never claim 5 V/5 A.
- Preferred full-power target: 12 V / 2.5 A = 30 W.
- Secondary target: 9 V / 3 A = 27 W.
Use ST NVM/GUI or the documented I2C NVM procedure to set exact voltage tolerance windows, operating current and mismatch handling, then read back and checksum/verify the programmed image. Hardware wiring does not program PDOs. On mismatch or unavailable preferred PDO, accept the best valid compatible lower profile, ultimately safe 5 V, and keep high loads unauthorized.
Safe load policy preserved from the U3 checkpoint:
- Unknown/default current: essential-only or shutdown; scanners and charging off.
- Valid 5 V/1.5 A: essentials only; scanners/charging disabled.
- Valid 5 V/3 A: staged scanners only within measured headroom; charging off or verified low rate.
- Valid 9 V/3 A or 12 V/2.5 A contract: U2 path enabled, but full-load authorization still requires valid contract/status and later load-switch policy.
Focused validation
- Direct pin/net inspection confirms every U1 pin is connected or intentionally no-connect, both grounds/EP are grounded, production passives are wired, CC dead-battery wiring is present, I2C address/pull-ups are defined, and U2 EN is no longer tied to raw VBUS.
- Focused keyword checks for STUSB, Q4, R36, R37, R39, and C60 returned no matching findings. The broad
U1keyword result is polluted by unrelated U11/U12/U13/U15/U16/U17/U18 designators; no U1 finding appeared in the returned scoped set. No scoped unexplained ERROR/WARNING/OPEN/UNCERTAIN remains. - Existing unrelated global ERC/SLC findings were not changed or waived.
Required bench and firmware tests
- Program NVM, power-cycle, read back PDO/NVM image, and confirm 0x28 I2C access after NVM load time.
- Test attach in both cable orientations and with default-current, 1.5 A, 3 A, 9 V/3 A and 12 V/2.5 A sources.
- Confirm U2 remains off with no cable, during U1 reset, failed negotiation, detach, brownout and source removal; confirm ordinary valid 5 V attach enables it.
- Scope VBUS_EN_SNK, Q4 base/collector, U2 EN/OUT, ATTACH_N and ALERT_N through attach/detach/hard reset/lower-PDO transitions.
- Verify receptacle and protected-side discharge timing and resistor pulse temperature at 20 V; confirm no backfeed.
- Measure I2C rise times at 400 kHz with the assembled bus.
- Exercise mismatch/reject/error recovery and verify scanners/charger remain unauthorized until firmware validates source current/contract.
Final project objective
Compact approximately square editable production PCB, upfront I2C support, red solder mask, white silkscreen, and a complete manufacturing package only after schematic and layout approval.
Scope and completion time
Final production parts
Connectivity and safe-state behavior
PD sink PDO/NVM policy
Focused validation
Required bench and firmware tests
Final project objective
