TPS259474 Protection Completion Checkpoint
Status
ARCHITECTURE BLOCKED — no schematic mutation performed. This checkpoint records the mandatory first-gate result for U2, U4, U7, and U9 only.
Timestamp and authoritative source
- Review date: 2026-07-23.
- Source: Texas Instruments TPS25947xx Rev. C datasheet, current TI product-family document for TPS259474LRPWR (
https://www.ti.com/lit/ds/symlink/tps25947.pdf).
- Installed part: TPS259474LRPWR, latch-off circuit-breaker variant, RPW 10-pin QFN.
Variant and pin-function verification
TPS259474LRPWR is the TPS259474x variant:
- Pin 1 EN/UVLO: active-high enable and adjustable UVLO analog input; must not float.
- Pin 2 OVLO: adjustable overvoltage-lockout analog input and active-low disable. It is not OVCSEL on this variant.
- Pin 3 PG: active-high open-drain power-good output. It is not AUXOFF on this variant.
- Pin 4 PGTH: analog power-good threshold input. It is not FLT on this variant.
- Pin 5 IN; pin 6 OUT; pin 7 DVDT slew-rate programming; pin 8 GND; pin 9 ILM current-limit programming/monitor; pin 10 ITIMER overcurrent blanking capacitor.
Key verified electrical behavior
- Recommended VIN: 2.7–23 V; continuous switch current: 5.5 A with TJ ≤125 °C.
- Integrated back-to-back MOSFETs are common-drain and block OUT-to-IN reverse current under all conditions.
- Ideal-diode loop regulates forward drop: VFWD = 4.7–16.9 mV at 10 mA.
- Fast reverse-block entry: VIN−VOUT = −36.45 to −22.3 mV (−29.3 mV typical).
- Fast recovery / full forward turn-on after reverse blocking requires VIN−VOUT = 83–125 mV (104.1 mV typical).
- Reverse leakage at VOUT−VIN = 21.5 V: 10.1 µA typical; on-state RCB output leakage with VOUT=VIN+1 V: 234 µA typical.
- UVLO/OVLO/PGTH rising threshold: 1.183–1.223 V; falling threshold: 1.076–1.116 V.
- ILM equation:
RILM(Ω) = 3334 / ILIM(A); allowed RILM range 549–6650 Ω.
- DVDT equations:
SR(V/ms)=IINRUSH(mA)/COUT(µF) and CDVDT(pF)=2000/SR(V/ms).
- TPS259474 circuit breaker starts ITIMER discharge when IOUT>ILIM and below 2×ILIM; persistent overload trips after
tITIMER = ΔVITIMER × CITIMER / IITIMER; fast trip applies at approximately 2×ILIM. The L suffix latches persistent overcurrent and thermal faults until VIN is cycled to 0 V or EN/UVLO is pulled below the shutdown threshold, not merely below UVLO.
- Thermal shutdown: 154 °C typical with 10 °C hysteresis; L variant remains latched off after cooling until reset.
- RPW thermal data: RθJA 41.7 °C/W on TI custom 4-layer board with eight thermal vias; 74.5 °C/W on JEDEC 4-layer board without thermal vias. Production thermal performance therefore depends strongly on exposed-pad copper/vias.
Live architecture inspection
The live schematic currently implements:
VBUS_RAW → U2 → VBUS_PROTECTED → U3 → USB_5V → U4 → SYS_5V.BAT_PROTECTED → U7 → BAT_BOOST_IN → U8 → BAT_5V → U9 → SYS_5V.- U4 OUT and U9 OUT are tied at
SYS_5V.
- U3 checkpoint specifies USB_5V ≈5.06 V; U8 divider targets BAT_5V ≈5.0 V.
- U2 EN is connected to the completed active-high
USB_EFUSE_EN path through Q4/R43.
- Present U2/U4/U7/U9 support is incomplete: OVLO and PGTH are unconfigured; PG status nets have no pull-ups; EN/UVLO on U4/U7/U9 is tied directly to input rather than calculated threshold networks; R1–R4 and C1–C8 remain generic; U4 input is still named
Net 1 rather than verified USB_5V connectivity in the direct U4 inspection.
Mandatory tied-output gate result — REJECTED AS UNPROVEN
The proposed source priority relies on only about 60 mV nominal offset (USB_5V ≈5.06 V versus BAT_5V ≈5.00 V) while both U4 and U9 remain enabled.
That offset can force U9 into reverse-current blocking when USB is established, because SYS_5V can exceed BAT_5V. However, after U9 has entered reverse blocking, TI guarantees fast return to full forward conduction only when BAT_5V − SYS_5V exceeds 83 mV minimum and as much as 125 mV. Therefore a 5.000 V battery source may require SYS_5V to fall to approximately:
- 4.917 V using the minimum 83 mV recovery threshold;
- 4.896 V at the 104.1 mV typical threshold;
- 4.875 V at the 125 mV maximum threshold.
The proposed 60 mV source offset is 23 mV below even the minimum guaranteed recovery threshold and 65 mV below the maximum threshold. The datasheet supports safe reverse-current blocking and ORing, but it does not prove interruption-free handoff at this offset without allowing a 83–125 mV SYS_5V droop and validating the recovery time, load transient, and rail hold-up.
No verified SYS_5V minimum operating requirement, effective SYS_5V capacitance at bias, worst-case load step, U9 recovery time waveform margin, or hold-up calculation is available in the scoped evidence. Consequently, make-before-break/no-brownout behavior and absence of oscillatory source interaction cannot be guaranteed from the present architecture. Per the task stop rule, no component/value/net mutation was made and no workaround or delayed shutdown control was added.
Source-state conclusions at this gate
- No source: reverse blocking prevents output backfeed in principle; final off-state depends on completed EN/UVLO networks.
- Battery only / USB only: individually feasible in principle, subject to completing each block.
- Both valid: USB should have priority because its input is higher; momentary linear-region sharing is possible near crossover. DC reverse current into BAT_5V is blocked, with datasheet leakage rather than cross-charge current.
- USB removal: safe reverse blocking by U4 is supported, but seamless U9 takeover is not proven because U9 recovery needs 83–125 mV forward differential.
- USB only/no battery: U9 reverse blocking is supported, but unpowered-input leakage and boost disable behavior still require bench validation.
- Weak USB with battery present: without a proven crossover/hold-up and downstream load policy, overload recovery or repeated fault interaction is unresolved. TPS259474L faults latch rather than auto-retry, but UVLO/OVLO recovery can still restart with dV/dt.
Scoped validation result
- No mutation occurred, so no caused ERC/SLC findings exist.
- Per instruction, no global ERC was run.
- Focused ERC/SLC was not run because the mandatory architecture gate failed before mutation; the known incomplete pins/support networks remain intentionally unchanged and are not claimed complete.
Exact blocker and next action
Blocker: the 60 mV nominal USB-over-battery offset is smaller than the TPS259474 guaranteed 83–125 mV forward-recovery threshold after reverse blocking. Seamless handoff cannot be proven without rail droop/hold-up evidence.
Next exact action before any TPS block completion: establish the minimum allowable SYS_5V at every load, measure or calculate worst-case USB-removal load step, obtain effective SYS_5V capacitance versus DC bias/tolerance/temperature, and prove that SYS_5V remains above that minimum through the 83–125 mV crossover plus worst-case TPS259474 recovery time. If that cannot be proven, revise the source-selection architecture or voltage offset with a TI-supported priority-mux method/device before setting U2/U4/U7/U9 passives.
Remaining bench/layout tests if architecture is later approved
- USB-removal and insertion handoff at minimum/maximum temperature, minimum BAT_5V, maximum load step, and worst-case capacitance.
- Reverse leakage/cross-charge into disabled U3/U8 paths.
- Crossover oscillation and current sharing with source tolerances and converter loop dynamics.
- UVLO/OVLO corners, dV/dt/inrush, ITIMER trip energy, short-circuit latch/reset behavior, PG timing, and thermal rise.
- RPW exposed-pad copper and eight-thermal-via implementation plus 5 A temperature validation.
Capacity / ACU
Remaining ACU count is not exposed by the available project tools.