Schematic Completion Pass 1 Checkpoint
Purpose
This file preserves the exact corrected-project stop point and resume order. Do not restart or rebuild the project. Preserve all existing schematic edits, component assignments, net names, architectural decisions, and unresolved items.
Project status
- Production status: STOP-SHIP.
- Corrected schematic: partial; not independently reviewable.
- PCB layout and manufacturing outputs: not authorized.
- Resume from the current live schematic state.
Completion Pass 1 — completed
- Added exact 0451010.MRL 10 A Littelfuse as F1.
- Assigned J2: pins 1/2
BAT_RAW; pin 3 PACK_NTC; pin 4 PACK_ID; pins 5/6 GND.
- Added FS8205A dual N-MOSFET and wired the LTC4365 protection path.
- Added provisional LTC4365 divider: 162 kΩ / 137 kΩ / 1.11 MΩ, targeting approximately 3.0 V UV and 4.35 V OV; tolerance validation remains required.
- Completed major BQ25895 power connections: both BAT, SYS, SW and PGND pins; 1 µH charger inductor; 20 µF nominal
CHARGER_SYS_LOCAL; BAT, REGN, PMID and BTST capacitors; 260 Ω ILIM; 5.23 kΩ / 30.1 kΩ TS network to PACK_NTC; /CE pulled high through 10 kΩ on CHARGER_EN_N; DPDM, OTG and DSEL intentionally NC.
- Added TPS259474 support on U2/U4/U7/U9: 665 Ω ILIM (approximately 5 A), 3.3 nF dV/dt, 2.2 nF ITIMER, and separate PG/status nets.
- Added TPS61288 support: Coilcraft XAL1060-222 2.2 µH 20 A-rated inductor; VIN bypass and bulk capacitance; VCC and BST capacitors; three 22 µF output capacitors; 73.2 kΩ / 10 kΩ feedback for approximately 5.0 V; provisional 36.5 kΩ compensation resistor.
- Confirmed major source topology remains separate and reverse-blocked:
VBUS_RAW → VBUS_PROTECTED → USB_5V → U4 → SYS_5VBAT_PROTECTED → U7 → BAT_BOOST_IN → U8 → BAT_5V → U9 → SYS_5VCHARGER_SYS_LOCAL remains isolated from SYS_5V.
- No PCB-layout changes were made.
Unresolved / blocking verification
- U3 TPS552882 remains substantially unwired. At the checkpoint, ERC reported at least 25 U3 floating pins. External buck-side MOSFET selection was unresolved because verified supported library parts were not available during the pass. Do not invent parts.
- U10 LMR33630 remains incomplete, with SW, BOOT, VCC, EN and PG floating.
- STUSB4500 reset, address, discharge, control and status wiring is incomplete.
- TPS259474 UV/OV and PGTH divider networks remain incomplete.
- TPS61288 compensation capacitors and hardware USB-present shutdown/recovery logic remain incomplete.
PACK_ID_ADC divider remains incomplete.- PACK_NTC, fan, scanner-node and peripheral wiring remain incomplete.
- Generic-passive package and footprint assignments remain incomplete.
- Visual wire/symbol collisions remain.
ERC evidence at checkpoint
- U3-scoped review: 25 errors, primarily floating support and power-stage pins.
- U10-scoped review: 6 errors, including missing VCC power.
- Overall power scope does not satisfy production verification criteria.
- No ERC error may be waived without written engineering justification.
Mandatory resume order
When execution capacity is available, perform one focused schematic-completion pass in this order:
- Verify the USB, charger and battery source-selection topology with a power-state table. Confirm uninterrupted operation while charging, no back-feeding, and safe USB insertion/removal.
- Complete U3 TPS552882 using verified manufacturer reference circuitry and supported external MOSFETs. Do not invent parts.
- Complete U10 LMR33630 and all required support components.
- Finish STUSB4500 control, reset, discharge, status and PD circuitry.
- Finish all TPS259474 UV/OV/PGTH networks and verify reverse-current blocking.
- Finish TPS61288 compensation and USB-present shutdown/recovery control.
- Complete PACK_ID, PACK_NTC, fan, scanner-node and peripheral wiring.
- Assign verified packages and footprints to every component.
- Remove schematic collisions and clear every ERC error. Do not waive an error without written engineering justification.
Required completion report
At the end of the focused completion pass, provide only:
- Final ERC results
- Power-state table
- USB and battery power budgets
- Remaining measurements or owner decisions
- Confirmation whether the schematic is ready for independent review
Approval gate
Do not begin PCB layout or create manufacturing files until the owner approves the completed schematic.
Resume attempt checkpoint — TPS552882 power-stage progress
- Verified from the TI TPS25947 datasheet that TPS259474 has integrated back-to-back MOSFETs and blocks OUT-to-IN reverse current under all conditions; U4/U9 remain architecturally suitable for 5 V source ORing.
- Verified the TI TPS552882 9–20 V to 5 V / 5 A reference design: 4.7 µH inductor, 10 mΩ output sense, 400 kHz, 5.2 V gate drive, and external buck-side N-channel MOSFET requirements.
- Added real Flux-library-supported TI CSD17578Q5A MOSFETs Q2/Q3 (30 V, 25 A, 6.9 mΩ, 7.9 nC, TDSON-8) as the TPS552882 high-side and low-side buck FETs.
- Wired Q2/Q3 half bridge: Q2 drain to VBUS_PROTECTED; Q2 source/Q3 drain/U3 SW1 to U3_SW1; Q3 sources and U3 PGND/AGND to GND; gates to DR1H/DR1L.
- Wired existing TI-recommended Coilcraft XAL1010-472MED L1 (4.7 µH) between U3_SW1 and both U3 SW2 pins.
- Fresh exhaustive review after these mutations: 316 unresolved findings at 2026-07-23T21:09:47.931Z, down from 326. U3/L1/Q2/Q3 power-stage wiring resolved 20 floating-pin findings; remaining findings are still dominated by floating pins plus missing-power and schematic-legibility issues.
- No PCB/layout or manufacturing mutation was performed. Q2/Q3 remain unplaced on PCB intentionally because PCB work is forbidden.
Next exact action
Continue mandatory step 2 by completing the remaining TPS552882 TI reference network: 10 mΩ sense between ISP/ISN, 4×10 µF input, 4×22 µF output, 4.7 µF VCC, both 100 nF bootstrap capacitors, 49.9 kΩ FSW, 19.9 kΩ ILIM, 29.4 kΩ MODE, 100 kΩ CDC, 150 kΩ/6.19 kΩ FB divider, compensation network, EN/UVLO, PG pull-up/destination, DITH/SYNC state, and CC_N requirement. Then re-run U3-scoped ERC before proceeding to U10.