Job 3G1 Correction
Thought for 35 sec
Thought for 11 sec — Inspecting project components
Reading layout details of LTC4373HDD#TRPBF.
Looking at the board of LTC4373HDD#TRPBF.
Reading symbol pins.
Thought for a moment
Analyzing pin layout issues
I see that there are problems with the EP terminal, which was generated as a perimeter pin, and the thermal pad being unbound. The project is HellzGate, but I can't mutate external components. I wonder if I can fix it by checking the part layout or submitting a quality issue. The pin placement seems incorrect too: the left row should have pins ordered as OUT 1, GATE 2, SOURCE 3, IN 4, while the right row has issues with UV and EP placements as well. This definitely needs attention!
Addressing thermal pad issue
Oh no, the thermal pad is separate and
there are two pads "IN_5" and "GND_4" which look like they should simply be GND
Thought for 11 sec
Those pads indicate the TPS259830ONRGER, not the LTC4373. They must not both be GND:
IN_5/ Thermal Pad 1 → INGND_4/ Thermal Pad 2 → GND
TI specifies two electrically distinct exposed pads; shorting both to GND would directly short the input rail. The footprint naming may be awkward, but that separation is electrically required.
Audit both footprints
Fix LTC4373 part
Inspect TPS259830 part
Remove bad LTC4373
Create repair plan
Refine this doc
Ask about this doc
Project Specification - HellzGate ESP32-C5 Node Cluster
Project Overview
Production-intent correction of the ESP32-C5 Node Cluster V2 carrier. Status: Conditionally approved for corrected schematic; STOP-SHIP for layout and manufacturing.
Intended Use
Portable wireless-surveying device with one coordinator and nine passive-scanning nodes, GPS, microSD, OLED, temperature-controlled fan, removable protected battery pack, and USB-C power/service access.
What the Device Should Do
- Power ten XIAO ESP32-C5 modules simultaneously for passive Wi-Fi/BLE scanning.
- Operate from a qualified USB-C source or one approved removable 1S battery pack.
- Operate normally while charging.
- Record survey data to microSD and provide GPS position.
- Use the coordinator to manage nodes over I2C.
- Fail safely during thermal, battery, source-power, or firmware faults.
Main Features
- 1 coordinator plus 9 scanner nodes
- 30 W-class USB-C PD with 5 V fallback
- 3000-9000 mAh approved 1S pack variants
- Managed charging and source ORing
- 5 V / 5 A USB-powered system capability
- Battery-mode power ceiling preserving all-node passive scan
- ATGM336H-5N31 GPS with active/passive antenna population options
- microSD, OLED, fan, diagnostics, and scanner OTA updates
System Architecture
Diagram
Hardware Subsystems
Battery
- One Molex Micro-Fit 3.0 six-pin pack interface.
- Two BAT+, two BAT-, PACK_NTC, PACK_ID.
- Approved complete 1S1P/1S2P/1S3P protected packs only.
- 5 A continuous / 10 A pulse provisional qualification.
- No user-parallel independent packs.
USB and Charging
- Standalone PD sink, VBUS TVS/eFuse, wide-input 5 V / 5 A converter.
- BQ25895-class managed 1S charger supplied from regulated USB 5 V.
- Charge disabled by hardware until pack and source validation.
Power Distribution
- USB 5 V and battery-boost 5 V reverse-blocked and ORed.
- XIAO modules powered only through VBUS.
- Quiet peripheral 3.3 V synchronous buck.
- Current-limited staged node startup.
Communications
- D4/SDA and D5/SCL retained.
- Coordinator is the only I2C master.
- Scanner branches segmented with I2C switches/buffers.
- Central USB-UART for coordinator diagnostics; I2C application OTA for scanners.
GPS
- ATGM336H-5N31 only.
- Active antenna default: 47 nH VCC_RF bias.
- Passive antenna supported through DNP population option.
- 50 Ohm controlled route on four-layer PCB.
Fan and Thermal
- 5 V ACP2006 fan on protected filtered branch.
- Coordinator control plus hardware fail-on thermal override.
- Fan remains available during all power-limit modes.
Interfaces and Connections
- USB-C: power, PD CC, USB 2.0 diagnostics.
- Battery: Micro-Fit six-pin managed pack interface.
- Fan: CN1/XH-2A, 5 V two-wire.
- GPS antenna: RF1 50 Ohm connector, final cable/antenna TBD.
- XIAO modules: socketed or manually fitted; VBUS, GND, D4/D5 and assigned peripheral pins.
Power and Runtime Expectations
- Normal scan envelope: 7.9 W at SYS_5V.
- Engineering USB peak: 23.1 W at SYS_5V.
- Full-power source: 30 W-class PD.
- Battery continuous ceiling: approximately 13 W at depleted 3.0 V with a 5 A input limit and 88% conversion assumption.
- Approximate 3000/6000/9000 mAh runtime at normal envelope: 1/2/3 hours.
Power Tree and Power Budget
Table
| Mode | Source | System limit | Charging |
|---|---|---|---|
| Full USB | Qualified 30 W PD | 5 V / 5 A rail class | Dynamic, system priority |
| USB 5 V / 3 A | Type-C 15 W | Normal scan, limited margin | Low rate or off |
| USB 5 V / 1.5 A | Type-C 7.5 W | Battery supplement or reduced load | Off |
| Battery | Approved 1S pack | All-node passive scan; TX peaks scheduled | Not applicable |
Manufacturing and Assembly Expectations
- Four-layer, 1.6 mm economical FR-4.
- L2 uninterrupted GND; L3 power distribution.
- Exact stackup selected before impedance routing.
- XIAO modules may be hand-fitted; BOM/DNP policy must be explicit.
- Optimize placement and footprints for reliable automated/manual assembly, optical inspection, solderability, and unambiguous component orientation.
- Verify all fabrication clearances and assembly access before manufacturing release.
- No manufacturing exports until corrected schematic and layout review are complete.
Firmware-Relevant Hardware Requirements
- Conservative startup with scanner loads disabled until source capability is known.
- Pack ID and NTC validation before charging.
- BQ charger register initialization before
/CEenable. - Battery-mode transmit scheduling and SD-write staggering.
- Coordinator diagnostics through USB-UART.
- Scanner application OTA over segmented I2C with recovery through module USB or fixture pads.
- Fan defaults to safe operation on reset, over-temperature, sensor failure, or firmware failure.
Physical Design Expectations
- Preserve approximately 88 mm x 88 mm board outline.
- Preserve external connector locations where electrically and mechanically practical.
- XIAO antenna keepouts apply on all layers.
- GPS/RF area separated from fan and switching converters.
- Power inductors and thermal copper may require small connector shifts.
- Co-design the PCB with the enclosure rather than treating the enclosure as a later step.
- Validate case walls, standoffs, screws, airflow, assembly order, cable bends, tool access, and component height against the enclosure model before placement approval.
- Keep USB-C, microSD, buttons, programming/debug access, and other user/service interfaces accessible through the enclosure without interference.
- Place RF connectors at board edges whenever practical; keep RF feed traces short/direct, separate RF connectors to reduce coupling, and prohibit noisy digital or switching-power routing beneath RF sections.
- Separate heat-generating regulators, chargers, power MOSFETs, and inductors from RF circuitry and provide adequate airflow and thermal copper.
- Prefer socketed/header-mounted replaceable modules where practical, including ESP32 modules, GPS, displays, sensors, and future expansion hardware.
- Keep serviceable components accessible without complete device disassembly and leave room for cables, connectors, probes, and hand tools.
- Provide accessible programming/debug headers and test points for all power rails, UART, I2C, reset, and boot.
- Reserve unused GPIO and provide expansion headers or pads where practical for future module compatibility and upgrades.
PCB Decision Priority — Locked
Apply this order when PCB constraints conflict:
- Electrical correctness
- Mechanical fit within the enclosure
- RF performance
- Manufacturability
- Serviceability and repairability
- Modular upgrades
- Ease of assembly
- Routing aesthetics
Do not optimize solely for shortest traces when that would reduce enclosure compatibility, service access, repairability, or upgradeability. Shortest-path routing remains mandatory for electrically critical RF, switching-current, timing, and signal-integrity loops.
Important Design Decisions
- Separate full-power USB 5 V path from battery charging path.
- Do not pass full system power through BQ25895 SYS/BATFET.
- One standardized complete battery pack at a time.
- Full 25 W available from qualified USB, not guaranteed from battery.
- Four-layer architecture and layered protection are mandatory.
Assumptions
- Exact battery MPN, OLED current, SD current, antenna/cable, fan stall current, ambient limit, and final fab stackup remain pending.
- Current budgets use official ESP32-C5 chip data plus conservative conversion assumptions until measured firmware data exists.
Change Notes
- Replaces unsafe V2 direct battery paralleling, TP4056 charger, paralleled LDO outputs, and XIAO 3V3 backfeed.
- Adds controlled battery interface, PD input, dual-source 5 V ORing, segmented I2C, fail-safe fan control, and configurable GPS antenna support.
Project Overview
Intended Use
What the Device Should Do
Main Features
System Architecture
Hardware Subsystems
Battery
USB and Charging
Power Distribution
Communications
GPS
Fan and Thermal
Interfaces and Connections
Power and Runtime Expectations
Power Tree and Power Budget
Manufacturing and Assembly Expectations
Firmware-Relevant Hardware Requirements
Physical Design Expectations
PCB Decision Priority — Locked
Important Design Decisions
Assumptions
Change Notes
