Job 3G1 Correction

Thought for 35 sec
Thought for 11 sec — Inspecting project components
Reading layout details of LTC4373HDD#TRPBF.
Looking at the board of LTC4373HDD#TRPBF.
Reading symbol pins.
Thought for a moment
Analyzing pin layout issues
I see that there are problems with the EP terminal, which was generated as a perimeter pin, and the thermal pad being unbound. The project is HellzGate, but I can't mutate external components. I wonder if I can fix it by checking the part layout or submitting a quality issue. The pin placement seems incorrect too: the left row should have pins ordered as OUT 1, GATE 2, SOURCE 3, IN 4, while the right row has issues with UV and EP placements as well. This definitely needs attention!
Addressing thermal pad issue
Oh no, the thermal pad is separate and
fatenerris

fatenerris

there are two pads "IN_5" and "GND_4" which look like they should simply be GND

flux

Those pads indicate the TPS259830ONRGER, not the LTC4373. They must not both be GND:
  • IN_5 / Thermal Pad 1 → IN
  • GND_4 / Thermal Pad 2 → GND
TI specifies two electrically distinct exposed pads; shorting both to GND would directly short the input rail. The footprint naming may be awkward, but that separation is electrically required.
Audit both footprints
Fix LTC4373 part
Inspect TPS259830 part
Remove bad LTC4373
Create repair plan

Refine this doc
Ask about this doc
Job 1 Schematic Implementation Change Log
HellzGate V2 Job 3G1 — Molex microSD replacement and south service-edge placement (2026-07-27)
Disposition: PASS for assigned Job 3G1 scope. Work began by atomically restoring checkpoint #4a24e477. Exact Molex 5033981892 was verified active against official drawing SD-503398-003; Flux/LCSC UID d8bf0227-1088-45ef-b6f8-dcdc193904e3 has the matching 8-contact, push-push, 1.28 mm-high footprint, card-detect contacts and a shared EH terminal for all four shell lands.
  • Replaced Yuandi TF-01A / C2889258 J3 while retaining designator J3. Final mapping: CD/DAT3→SD_SPI_CS, CMD→SD_SPI_MOSI, VDD→PERIPH_3V3, CLK→SD_SPI_SCK, VSS→GND, DAT0→SD_SPI_MISO; DAT2 and DAT1 remain explicit NC. Molex detect pads 9/10 are explicit reserved NC; EH (all four shell/mount lands) is GND. The Yuandi part is absent from schematic and BOM.
  • Final placement: J1 (-35.000, -54.755) mm, 0°, Top; J3 (+35.000, -53.730) mm, 0°, Top. Both face/insertion directions are toward −Y. J1 mating face and J3 card mouth are datum-aligned to Y=−60.000 mm; only verified footprint/mechanical overhang is outside the outline.
  • No staging moves were required. Exact moved list: J1 and replacement J3 only. X1 and U16–U24 were not moved; no routing, copper, outline, stackup/layer, power-architecture or unrelated schematic changes were made.
  • Final focused ERC/DRC/component-availability review returned no open warning/error findings for J1/J3. Schematic/PCB/BOM reconciliation shows one exact Molex J3. Existing unrelated whole-board placement/routing congestion remains outside this job.
Job 3G1 approval status: approved for the assigned replacement/placement scope; routing remains unauthorized.
HellzGate V2 Job 3D — controlled placement-feasibility pass (2026-07-27)
Disposition: FAILED / PROVISIONAL PLACEMENT FULLY REVERTED. The 88.000 mm × 88.000 mm foundation cannot accommodate the requested major-block architecture responsibly with the required service/removal/cable corridors and four corner reservations. The live PCB was restored to the pre-Job-3D checkpoint #5ffa65a2; no Job 3D component coordinates remain.
Foundation verification
  • Read-back confirmed the centered 88 × 88 mm rounded-square outline with 2 mm corners.
  • Exactly ten corrected XIAO socket footprints are present: X1, U16–U24. Each footprint exposes 14 distinct named pads (D0–D10, 3V3_OUT, GND, VBUS) rather than collapsed lands. Electrical reconciliation remained intact after the revert: all ten GND pads are on GND; X1 VBUS is on COORD_5V; U16–U18 VBUS are on SCAN_A_5V; U19–U21 VBUS are on SCAN_B_5V; U22–U24 VBUS are on SCAN_C_5V. Coordinator signal nets remain assigned and scanner pins 1–12 retain their prior explicit no-connect disposition.
  • Whole-schematic electrical review returned zero ERROR/WARNING/OPEN findings.
  • The accepted layer intent remains L2 future continuous GND and L3 primarily power. Job 3D did not retry copper-layer labels or NPTH creation.
Enforced analysis constraints
  • Reserved four analysis-only circular no-overlap regions, 5.0 mm diameter, centered at (−40,−40), (+40,−40), (+40,+40), and (−40,+40) mm. No physical holes, copper, or silkscreen were created.
  • Reserved USB-C edge access; internal GNSS U.FL-to-SMA pigtail and strain-relief space; coordinator service access; XIAO body, USB, socket-removal, and external-antenna-cable corridors; and routing/thermal expansion channels around the main switching island.
  • The exact service envelope of the ESP32-C5 onboard U.FL remains unknown. No U.FL position or directional keepout was invented; only conservative whole-body cable/service clearance was requested.
Provisional placement attempt and inspection
  • Scope was bounded to X1; U16–U24; J1; U2/U3/Q2/Q3/L1/R19; C40–C51, C60, C67–C73; U4–U7; U10–U15; L5; J_GPS; and J3. Unrelated parts were not authorized for general relocation.
  • Required architecture was submitted: USB-C at the lower edge; compact lower power island with capacitor banks and thermal-copper room; GNSS/U.FL at the opposite edge; microSD at an accessible edge; distinct coordinator service position; and ten usable XIAO removal/cable corridors clear of the U3 island and mounting reservations.
  • The placement engine could not converge. Its best provisional state placed only L1, J_GPS, and Q2 while still reporting component collisions, board-edge violations, blocked pad access, unsatisfied placement constraints, and many unplaced scoped parts. The attempt therefore failed the collision/clearance, edge-access, mounting-reservation, service/removal, RF/power-separation, thermal-area, routing-channel, and density gates.
  • The board-wide density read-back is 6305 mm² component area on 7744 mm² board area: 81.4% before routing/service reservations. It also classifies the current topology as unroutable and estimates at least 884 mm² of component area must leave the top side even before preserving the requested mechanical/service architecture.
Required dimensional or architectural change
  • Pure area math for a responsible 50% placement fill requires a square side of at least 6305/0.50=112.3 mm\sqrt{6305/0.50}=112.3\text{ mm}. Therefore the absolute minimum dimensional growth is approximately +24.3 mm per axis, rounded to at least 113 × 113 mm. Because the four corner reservations, USB/microSD edge access, GNSS-to-power separation, ten XIAO removal/cable corridors, and routing/thermal channels consume non-component area, 120 × 120 mm is the practical next feasibility target (+32 mm per axis).
  • If 88 × 88 mm must remain fixed, the exact architecture change required is to move the nine scanner XIAO sockets off the main PCB onto separate daughtercards/backplane-connected modules (or reduce the installed scanner count); simply moving small passives to the bottom does not create the required top-side XIAO service/removal area.
Revert and mutation audit
  • Reverted all 15 provisional placement commits in one operation to #5ffa65a2. Final moved-major-designator list: none; final Job 3D X/Y/rotation/layer coordinate table is empty because every provisional move was removed.
  • Post-revert layout read-back matches the pre-pass staging coordinates for the scoped majors.
  • No traces were added. No Job 3D vias or copper pours were added; the read-back still shows only the pre-existing GND fill and 24 pre-existing GND vias. No schematic, board outline, holes, silkscreen, or layer labels were changed.
Job 3D viability result: 88 × 88 mm does not pass. Placement is not retained; routing remains unauthorized.
HellzGate V2 Job 3C — PCB foundation checkpoint (2026-07-26)
Disposition: PARTIAL / BLOCKED. Only authorized PCB-foundation work was attempted; no routing or functional-group placement was performed.
  • Board outline mutated to the authoritative centered 88.000 mm × 88.000 mm rounded square, extents −44.000…+44.000 mm on X/Y, with 2.000 mm corner radius. Layout read-back reports 88 × 88 mm, rectangle, 2 mm radius.
  • The preserved four-layer direction and requested roles were submitted as L1 Top Signal / L2 solid Ground Plane / L3 Power Plane / L4 Bottom Signal. Stackup verification is blocked by inconsistent tool read-back: stackup-only inspection displays four copper layers but labels both inner layers Signal, while layout-tree inspection collapses the same named stackup to two copper layers. No impedance calculation or routing was performed, and the layer-role criterion is not claimed complete.
  • All ten required XIAO designators (X1, U16–U24) now read back as private UID cc51af47-885f-4448-b27d-0e502ea82234, with the XIAO-ESP32-C5-DIP.kicad_mod footprint present. The preserved checkpoint already contained the replacements but U17–U24 had lost connectivity/NC state. Restored terminal-equivalent mapping: every module pin 13→GND; X1 pin 14→COORD_5V; U16–U18 pin 14→SCAN_A_5V; U19–U21 pin 14→SCAN_B_5V; U22–U24 pin 14→SCAN_C_5V. Restored scanner pins 1–12 as explicit NC. Post-repair ERC reports no ERROR/WARNING findings, and the XIAO part count is exactly ten.
  • Four mounting holes remain blocked. Two attempts to instantiate the available Generic Non-Plated Mounting Hole at the authorized centers (−40,−40), (+40,−40), (+40,+40), (−40,+40) mm were rejected by the component mutation backend, which rewrote the valid library result to unavailable UID 0d2a39ed-69ef-4af7-acdb-c625aadbfe4a and dropped all four components. No substitute primitive was added because Job 3C requires reconciled Generic NPTH components, not inferred standalone pads.
  • Schematic-to-PCB reconciliation is exact for the ten corrected XIAO designators. Overall Job 3C reconciliation/approval remains blocked by the absent four mounting-hole components and contradictory stackup read-back. Existing staging component positions are not final and were not functionally placed.
Job 3C approval status: not approved / checkpoint preserved pending mounting-hole component backend repair and deterministic four-layer role read-back.
HellzGate V2 Job 2F1 — GNSS RF schematic implementation (2026-07-26)
Disposition: qualified GNSS RF schematic is implemented and whole-schematic ERC is clean. No PCB placement/routing, firmware, app, GateLink, power architecture, enclosure/outline, manufacturing, battery, fan or ESD changes were made.
Private exact bias component
  • Created private Murata LQW18AN47NJ00D, Flux UID 895f7013-0877-43e5-bbb1-4852a8eacb3d.
  • Verified 47 nH ±5%, 0603/1608 metric, 380 mA, 0.29 Ω maximum DCR, 2.6 GHz minimum SRF basis, two passive terminals, terminal 1→pad 1 and terminal 2→pad 2. Footprint lands are 0.8 × 0.8 mm on 1.15 mm pitch, 1.95 mm outside span. Sources: Murata JELF243A_0024AB-01, LQW18AN EDA library and MT_LQ3E mounting guidance.
Implemented RF block
  • Removed no-connect disposition from U15 RF_IN and VCC_RF.
  • Added LBIAS = exact Murata LQW18AN47NJ00D.
  • Added J_GPS = Hirose U.FL-R-SMT(10). Verified pad 2 is center/SIG; pads 1 and 3 are shell/GND.
  • Added R_GPS_PI = Stackpole RMCF0402ZT0R00, exact 0 Ω 0402 series jumper.
  • Added C_GPS_IN_SHUNT and C_GPS_OUT_SHUNT as 0402 RF-tuning shunt footprints, DNP by default and excluded from BOM/pick-and-place. No tuning capacitance was invented.
  • No series DC-block capacitor and no ESD device are present.
Net map
  • GPS_BIAS_SOURCE: U15 VCC_RF ↔ LBIAS pin 1.
  • GPS_RF_IN_MATCH: U15 RF_IN, input shunt DNP pin 1 and R_GPS_PI pin 1.
  • GPS_RF_BIASED: R_GPS_PI pin 2, output shunt DNP pin 1, LBIAS pin 2 and J_GPS center pad 2.
  • GND: both shunt DNP ground terminals and J_GPS shell pads 1/3.
  • The center conductor has no populated ground or DC-block path; the only shunt sites are DNP.
Default population

Table

RefPartDefault
LBIASMurata LQW18AN47NJ00DPopulate
J_GPSHirose U.FL-R-SMT(10)Populate
R_GPS_PIStackpole RMCF0402ZT0R00Populate
C_GPS_IN_SHUNTGeneric 0402 RF tuningDNP; BOM/P&P excluded
C_GPS_OUT_SHUNTGeneric 0402 RF tuningDNP; BOM/P&P excluded
Interface record
  • J_GPS is internal/service-only. Preferred internal pigtail is Taoglas CAB.719 to a standard SMA female bulkhead—not RP-SMA—labeled GPS ACTIVE ANTENNA — 3.3 V BIAS.
  • Supported external antenna is active GPS L1, standard SMA male, 50 Ω, 3.3 V bias compatible, 15–30 dB gain, safely below 50 mA. Pigtail requires enclosure strain relief and U.FL must not carry cable forces.
  • Molex 2066400001 remains a mutually exclusive optional internal antenna. No pigtail, bulkhead or antenna was added as a PCB component or assembled-PCB BOM item.
Verification and BOM
  • Focused GPS ERC: 0 electrical findings.
  • Whole-schematic ERC at 2026-07-26T22:58:31.105Z: 0 open electrical findings.
  • Exactly ten ESP32-C5 carrier interfaces remain; SCAN_A/B/C_CMD each retain three valid members.
  • Populated PCB BOM delta: LBIAS, J_GPS and R_GPS_PI only. Approximate one-off incremental cost is $0.33–$1.50 excluding shipping; shunt footprints have zero populated cost.
Approval gates
  • Preliminary PCB placement remains BLOCKED until the RF block can be placed with the bias tee/pi network adjacent to U15, short stub-free RF path, mechanically supported internal U.FL and low-inductance shell grounding.
  • Prototype fabrication remains BLOCKED until enclosure/bulkhead geometry, strain relief, final stackup-derived 50 Ω geometry and RF clearances are resolved.
  • Post-build VNA tuning, two antenna-position comparison, ten-radio coexistence and GNSS performance tests block production release, not initial prototype fabrication after pre-fabrication constraints are closed.
HellzGate V2 Job 2D1 — Final schematic cleanup and GPS closure (2026-07-26)
Disposition: digital/control cleanup is complete. Preliminary PCB placement and fabrication remain BLOCKED because the GPS RF architecture is not yet qualified. No PCB routing, firmware, app, GateLink, manufacturing, battery, MiniGate, or S3 changes were made.
Removed components
  • Removed optional fan connector CN1; both pins had zero net membership and no shared fan circuitry existed.
  • Removed confirmed orphan parts R8, R13, R14, R15, C32, C33, C34. Every terminal had zero live net membership; no connected circuitry was affected.
ATGM336H-5N31 digital/control disposition
  • Preserved U15 VCC and VBAT on PERIPH_3V3, all three grounds, root-I²C SDA/SCL, and C76 10 µF bypass.
  • Marked TXD, RXD, 1PPS, NRESET and ON/OFF explicit reserved/no-connect. Manufacturer documentation permits NRESET floating when unused; ON/OFF is left open in normal-operation application circuits; unused TXD/1PPS outputs and RXD command input require no external bias in the reference application.
  • Literal NC and RESERVED pins remain explicit no-connect.
GPS RF research and decision
  • Exact module documentation supports both active and passive antenna approaches. VCC_RF is a nominal 3.3 V antenna-power output; the reference active-antenna path uses a 47 nH feed element, with documented open/short detection around 3 mA/50 mA and active-antenna gain guidance of 15–30 dB.
  • The documented passive approach is not a bare chip antenna directly on RF_IN; it uses an external AT2659 LNA and the manufacturer-shown 6.8 nH, 470 pF and 0.1 µF network.
  • A possible Abracon ACAG0301-1575-T passive GPS-L1 chip antenna exists, but it was not added. Its corner position, ground-plane size, keepout, board-stack translation and board-specific matching have not been qualified for the approximately 88 × 88 mm enclosure or the ATGM336H front end.
  • RF_IN and VCC_RF therefore remain unchanged. Required evidence before mutation: enclosure material and antenna location/orientation, final stackup, vendor reference-layout translation, exact matching/LNA topology, and a VNA/tuning/OTA validation plan. RF feed must be controlled 50 Ω, short, isolated from switching/digital noise, and implemented with the selected antenna vendor’s exact ground/keepout geometry.
Final ERC

Table

CategoryErrors
Floating Pin2
Missing Power0
Driver Conflict0
Single-Pin Nets0
Scanner-command errors0
Total2
The only remaining findings are deliberate RF blockers: U15:RF_IN and U15:VCC_RF. No fan or battery circuitry remains.
Remaining gates
  • RF: select and qualify the exact GNSS antenna/LNA/bias/matching architecture and layout geometry.
  • Simulation: U3 loop/transient/thermal, eFuse timing, supervisor/fault-latch sequencing.
  • Bench before fabrication: STUSB NVM readback, branch inrush/fault/no-backfeed, CP2102N power-order/enumeration/leakage, TCA9548A address/brownout reset, GPS I²C position data, GNSS sensitivity/fix/OTA performance, and thermal validation.
Job 2D1 approval: preliminary PCB placement BLOCKED; fabrication BLOCKED.
HellzGate V2 Job 2D — Schematic blocker closure (2026-07-26)
Disposition: deterministic Job 2C blockers were closed, but PCB placement remains BLOCKED by 23 unresolved floating-pin findings and outstanding qualification gates. No PCB/layout/routing/outline, firmware, app, GateLink, manufacturing, battery, charger, boost, source-selector, MiniGate, or S3 changes were made.
CP2102N U14
  • Verified CP2102N-A02-GQFN24 and implemented Silicon Labs-supported self-powered regulator-bypass mode: VDD = VREGIN = VIO = PERIPH_3V3. This keeps U14 off when the system peripheral rail is absent rather than powering the bridge directly from USB.
  • Replaced direct VBUS_RAW sensing with VBUS_RAW -> R83 22.1 kΩ -> U14_VBUS_SENSE -> R84 47.5 kΩ -> GND, with the midpoint connected to U14 VBUS. This follows the powered-off leakage/current-limiting reference approach.
  • Added R85 RC0603FR-071KL, 1 kΩ, from RSTb to PERIPH_3V3.
  • Added 4.7 µF + 100 nF local bypass pairs on VDD, VREGIN and VIO: C80/C82/C84=0603B475K100NT; C81/C83/C85=C0603C104K4RACTU.
  • Marked literal NC pins and unused modem-control/GPIO/suspend pins explicit no-connect. USB D+/D−, UART, VIO and VBUS sensing were preserved. U14-focused ERC is clean.
TCA9548A U11/U12
  • Confirmed all downstream SCx/SDx channels were genuinely unused and marked them explicit no-connect.
  • U11 address: A2=A1=A0=GND, 7-bit 0x70.
  • U12 address: A2=A1=GND, A0=PERIPH_3V3, 7-bit 0x71.
  • RESET is deterministically high through R86/R87 0603WAF1002T5E, 10 kΩ, to PERIPH_3V3. TI POR/reset behavior deselects all channels at startup. Added C86/C87 CC0603KRX7R7BB104, 100 nF, VCC-to-GND. Root bus and existing 4.7 kΩ pullups were preserved.
ERC disposition
  • Marked all 99 unused scanner GPIO pins on U16–U24 reserved/no-connect; VBUS and GND unchanged.
  • U15 GPS: marked only literal NC_1, NC_2, RESERVED_1, RESERVED_2 no-connect. Left VCC_RF, RF_IN, NRESET, ON/OFF, TXD, RXD and 1PPS unchanged because they require an approved antenna/interface/control decision.
  • J3 SPI-only microSD: DAT1, DAT2 and separate mechanical CD marked no-connect; CD/DAT3 remains SPI CS.
  • U9 Q was disconnected and marked no-connect; orphan POWER_FAULT_LATCH deleted. NOT_POWER_FAULT_LATCH on ~Q remains active.
  • CN1, R8, R13–R15 and C32–C34 were not removed because their purpose cannot be proven from live connectivity or authoritative records.
Whole-schematic ERC

Table

CategoryJob 2C baselineJob 2D final
Floating Pin18423
Missing Power10
Single-Pin Nets10
Driver conflicts00
Total18623
Final 23: U15 GPS/RF/control 7; CN1 provisional fan connector 2; R8/R13/R14/R15 and C32/C33/C34 fully orphaned pins 14. Scanner command nets remain clean and no battery path was reintroduced.
Evidence required and qualification gates
  • Approve a GPS antenna architecture and decide whether reset, ON/OFF, UART and 1PPS are used. Do not invent RF bias or a 50 Ω path.
  • Supply the production fan specification/requirement or authorize CN1 removal.
  • Supply a prior net snapshot/design record establishing the orphan passive purpose, or authorize deletion.
  • Bench: CP2102N enumeration/UART under USB-only, PERIPH-only, simultaneous-power and removal-order cases; powered-off VBUS-sense leakage/backfeed; U11/U12 address readback and brownout reset; existing STUSB NVM, U2/U3/branch startup, fault injection, thermal and no-backfeed testing.
  • Simulation: existing U3 loop/transient/thermal, eFuse timing and supervisor/latch sequencing gates remain open.
Final Job 2D status: BLOCKED for PCB placement.
V2 Job 2C — Complete schematic approval review (2026-07-26)
Disposition: Direct-PD Job 2B/2B1 core is conditionally accepted, but PCB placement is BLOCKED. No PCB, layout, firmware, app, GateLink, outline, routing, or manufacturing data was modified.
Authorized correction
  • Commit #f1342d29: marked verified-unused U13 P03–P17 and ~INT explicit reserved/no-connect. Preserved P00/P01/P02 -> SCAN_A/B/C_CMD, R56–R58 10 kΩ pulldowns, A0/A1/A2=GND (0x20), PERIPH_3V3 and root-I²C. Fourteen U13 floating-pin findings were resolved.
Architecture audit
  • Product boundary confirmed: one X1 ESP32-C5 coordinator and nine U16–U24 ESP32-C5 scanners; no S3, battery, charger, boost, battery connector, source selector, or MiniGate power path.
  • Main path confirmed: J1 VBUS -> VBUS_RAW -> U2 TPS259474L -> VBUS_PROTECTED -> U3 TPS552882 -> U3_PRE_SHUNT -> R19 8 mΩ -> SYS_5V.
  • U3 confirmed at 5.100 V nominal using 32.5 kΩ/10 kΩ post-shunt feedback; exactly 8×10 µF input caps, 6×22 µF output caps, C67 100 µF bulk, 150 kΩ + 10 nF compensation, no U3_PG net, and hardware-qualified/default-low enable.
  • Branch map confirmed: U4→X1; U5→U16–U18; U6→U19–U21; U7→U22–U24. Each XIAO VBUS belongs to exactly one branch and all module grounds are GND. Commands remain fail-safe and cannot bypass POWER_VALID or NOT_POWER_FAULT_LATCH.
  • U8 TPS3808 monitors SYS_5V with 110 kΩ/10 kΩ: approximately 4.860 V nominal trip. C74=10 nF gives approximately 57.64 ms nominal release delay. Full tolerance and asynchronous latch sequencing remain simulation/bench gates.
  • Root-I²C pullups are 4.7 kΩ to PERIPH_3V3. U13 is deterministic at 0x20. U11/U12 TCA9548A A0/A1/A2 and RESET are floating, so their addresses/reset states are undefined and may conflict.
  • U10 PERIPH_3V3, U15 VCC/VBAT+C76, microSD SPI mapping, and CP2102N USB/UART signal paths were verified. U14 CP2102N VDD and VREGIN are floating; the intended internal-regulator/bypass power mode must be selected from the datasheet before correction.
Whole-schematic ERC
ERC rerun at 2026-07-26T21:34:42.379Z:

Table

CategoryErrors
Floating Pin184
Missing Power1
Single Pin Nets1
Driver/pin/short/undriven/endpoint conflicts0
Total186
Primary classification: U11/U12 address/reset and channel pins 40 genuine unresolved; scanner module unused GPIO 99 pre-existing and undispositioned; U15 GPS/RF/control 11 mixed genuine/intentional; U14 15 mixed with VDD/VREGIN genuine; J3 DAT1/DAT2/CD 3 intentional but undispositioned; CN1 2 provisional; isolated R8/R13/R14/R15 and C32/C33/C34 14 unexplained/orphaned. Missing Power is U14 VDD. Single-pin net is POWER_FAULT_LATCH at unused U9 Q; active logic uses ~Q.
Placement unblock requirements
  1. Select and implement the approved CP2102N power mode, correcting U14 VDD/VREGIN.
  2. Assign deterministic nonconflicting U11/U12 addresses and RESET states; disposition unused mux channels.
  3. Disposition genuine GPS/RF, microSD, scanner-module, fan, and isolated-passive findings.
  4. Explicitly disposition U9 Q / POWER_FAULT_LATCH.
  5. Rerun whole-schematic ERC and close every genuine finding.
  6. Complete U3 stability/thermal/transient, U2/branch timing, supervisor/latch sequencing, STUSB NVM, cold-start, fault-injection, inrush, and no-backfeed qualification.
Firmware review items
  • Write U13 P00–P02 output latches low before configuring them as outputs, then enable banks sequentially.
  • Keep commands low through boot, brownout, I²C recovery and bus failure; verify U13 at 0x20 by readback.
  • Treat abrupt microSD power loss through journaling/flush/recovery; no hardware hold-up is claimed.
Final Job 2C status: schematic core CONDITIONAL PASS; BLOCKED for PCB placement.
V2 Job 2B1 — Existing U13 scanner-command completion (2026-07-26)
  • Verified U13 as TI TCA9535PWR, TSSOP-24, supplied from PERIPH_3V3 and connected to I2C_ROOT_SDA/SCL. Flux symbol pin numbers match the TI PW-package pinout. A0/A1/A2 are now tied directly to GND, selecting 7-bit I2C address 0x20.
  • TI specifies internal power-on reset with no external reset pin. All P-port pins power up as high-impedance inputs (Configuration Port 0/1 = 0xFF). Output latches default high, so firmware must first write Output Port 0 bits P00-P02 low, then configure those three bits as outputs; only afterward may it assert a requested scanner command.
  • Final command mapping is symmetric: U13 P00 -> SCAN_A_CMD, U13 P01 -> SCAN_B_CMD, and U13 P02 -> SCAN_C_CMD. Temporary X1 D2_GPIO25 -> SCAN_A_CMD was removed and X1 D2_GPIO25 returned to intentional no-connect/reserved status.
  • Added fail-safe command pulldowns: R56/R57/R58 are Yageo RC0603FR-0710KL, 10 kΩ ±1%, one from each SCAN_A/B/C_CMD net to GND. This holds all command requests low while U13 is unpowered, in POR, or still configured as high-impedance inputs.
  • Branch logic remains unchanged: branch enable = POWER_VALID AND SCAN_x_CMD AND NOT_POWER_FAULT_LATCH. Firmware cannot bypass hardware validity or the fault latch.
  • Focused connectivity/ERC: each scanner-command net has exactly three members (U13 port, branch gate input, pulldown) and no scanner-command single-pin-net finding remains. U13-focused ERC still reports the pre-existing unused P03-P17 and INT pins as floating; they are outside this narrow command correction and must be assigned, externally biased, or explicitly dispositioned before unconditional production approval.
  • Remaining qualification gates: firmware initialization/readback at address 0x20; cold-power and brownout tests proving all banks remain off until deliberate configuration; I2C bus-fault/recovery testing; branch enable/fault-latch timing; and final disposition of unused U13 ports/INT.
V2 schematic approval checkpoint: CONDITIONAL PASS for Job 2B1 command completion; overall production approval remains blocked by the listed ERC and bench/simulation gates.
Final narrow Job 2B coordinator/GPS correction (2026-07-26)
  • Direct pin-occupancy inspection found only one genuinely unused coordinator GPIO on the existing 14-pin XIAO carrier: X1 D2_GPIO25. It is now explicitly connected to SCAN_A_CMD; firmware mapping is GPIO25 -> SCAN_A_CMD / scanner bank A request. The branch equation remains POWER_VALID AND command AND NOT_POWER_FAULT_LATCH through the existing logic.
  • SCAN_B_CMD and SCAN_C_CMD could not be assigned without violating the narrow brief. Every other X1 GPIO is already committed: GPIO1 STUSB_ATTACH_N, GPIO0 STUSB_ALERT_N, GPIO7 SD CS, GPIO23/24 root I2C, GPIO11/12 service UART, and GPIO8/9/10 SD SPI. X1 3V3_OUT is a power pin, not a GPIO. Therefore two additional coordinator outputs require an explicitly approved pin-mux/interface change or a carrier with more GPIO; no existing signal was disturbed and no strapping/occupied pin was guessed.
  • U15 ATGM336H-5N31 datasheet permits VBAT=1.5–3.6 V and shows a 3 V backup source. For no separate backup battery, U15 VBAT is now tied to existing regulated PERIPH_3V3 (also U15 VCC), with new local C76 10 uF to GND as required by the manufacturer application circuit. No battery rail or battery component was introduced.
  • Focused ERC: SCAN_A_CMD clean; U15:VBAT clean; battery keyword clean. SCAN_B_CMD and SCAN_C_CMD each retain exactly one single-pin-net error because the carrier exposes no further unused GPIO under the stated preservation constraints.
Focused Job 2B completion pass (2026-07-26)
Scope: schematic only; no PCB/layout/firmware changes.
  • U2 ILIM is now exact Yageo RC0603FR-071K05L, 1.05 kΩ ±1%; datasheet equation gives 3.175 A nominal. Retained EN, 3.3 nF dVdt, 2.2 nF ITIMER, IN/OUT/GND, PG and PG pull-up. Added 164 kΩ/10 kΩ ±1% OVLO divider (20.88 V nominal; approximate independent threshold/resistor corner 20.22–21.57 V) and 56.2 kΩ/10 kΩ ±1% PGTH divider (7.944 V nominal), so 5 V fallback does not qualify while 12/15 V does.
  • U3 input bank is exactly C40–C47, eight CL32B106KBJNNNE, each VBUS_PROTECTED-to-GND. Removed the four floating excess instances. Output bank remains exactly C68–C73, six CL32B226KAJNNNE, each SYS_5V-to-GND. Direct inspection retained the post-shunt 8 mΩ path, 32.4 kΩ + 100 Ω / 10 kΩ feedback, and 150 kΩ + 10 nF compensation. No U3_PG net exists.
  • Wired C19–C28, ten 100 nF local logic bypass capacitors, from STUSB_VREG_2V7 to GND. Logic VCC/GND connectivity and existing decode/latch nets were retained. U8 MR is now defined high from SYS_5V; VDD, GND/EP, 110 kΩ/10 kΩ SENSE, 10 nF CT, RESET pull-up/SYS_5V_VALID and asynchronous latch PRE path remain connected.
  • U4–U7 received identical support: 35.7 kΩ/10 kΩ ±1% OVLO (5.484 V nominal), 30 kΩ/10 kΩ ±1% PGTH (4.8 V nominal), 10 nF dVdt (0.2 V/ms nominal; ~25 ms to 5 V), and 10 nF ITIMER (~8.4 ms nominal blanking, latch-off persistent fault). Existing EN pulldowns, PG pullups, GND, inputs/outputs, 2.49 kΩ ±1% scanner ILIM, and 3.83 kΩ coordinator ILIM were retained. Cold-start/inrush and coordinator current measurement remain production gates.
  • Direct VBUS map verified: X1=COORD_5V; U16–U18=SCAN_A_5V; U19–U21=SCAN_B_5V; U22–U24=SCAN_C_5V. Battery-keyword focused ERC returned no findings. Empty Net 1 and Net 3–6 were deleted; Net 2 and Net 7 deletion calls timed out and remain as empty zero-pin identifiers.
  • Focused ERC after mutation: no matching Job 2B findings for U4, U5, U6, U7, U8 or battery keywords. U2 support-pin floating findings were resolved. U3 keyword returns only three pre-existing scanner command one-pin nets (SCAN_A_CMD/B_CMD/C_CMD), outside this pass's assigned command-source scope. Module keyword matching still reports pre-existing unused XIAO GPIOs, explicitly excluded by the brief.
Remaining genuine blockers/gates: bench verification of U2 OVLO/PGTH full-temperature thresholds and ILIM; branch startup/inrush and persistent-fault timing; coordinator 0.87 A provisional ILIM; STUSB NVM PDO programming/readback; U3 compensation/transient validation. Local SLC geometry remains non-approval-blocking and was not expanded because new canonical-net stubs do not alter electrical connectivity.
V2 Job 2B direct-PD schematic execution (2026-07-26)
Disposition: PARTIAL / NOT SCHEMATIC-APPROVED. Pre-mutation checkpoint was #109b5f75. Scope remained schematic-only; no PCB/layout/routing/firmware/app/schema/manufacturing mutation was performed.
Architecture and power flow
  • Selected external USB-C PD only. Battery connector/protection/charger/boost/source-selector devices and their battery-only support were removed.
  • Direct power flow is J1 VBUS -> U2 TPS259474L -> VBUS_PROTECTED -> U3 TPS552882 -> 8 mΩ Kelvin shunt -> SYS_5V.
  • U3 PG support was removed, U3 PG is intentionally NC, and the U3_PG_N net was deleted. Buck regulation loss is observed only through SYS collapse/TPS3808.
  • STUSB policy contract recorded: PDO1 5 V fallback/negotiation only; PDO2 12 V/3 A; PDO3 15 V/3 A. NVM programming is a bench gate, not schematic wiring.
U3 and SYS values
  • R19 is exact HoJLR2512-3W-8mR-1%; calculated current limit from 48/50/52 mV is 5.94 A min / 6.25 A nominal / 6.57 A max including ±1% shunt corners.
  • Feedback upper is represented as 32.4 kΩ ±0.1% plus 100 Ω ±0.1% in series (32.5 kΩ total), with retained R25 RT0603BRE0710KL 10.0 kΩ ±0.1%, targeting 5.100 V nominal.
  • Compensation is exact R26 RT0603BRD07150KL 150 kΩ ±0.1% in series with C51 CGA3EAC0G2A103J080AC 10 nF ±5% C0G 100 V to GND. Samsung-model/PSpice stability remains a mandatory validation gate.
  • Input bank is 8 × Samsung CL32B106KBJNNNE 10 µF/50 V/X7R/1210 from VBUS_PROTECTED to GND. Output bank is 6 × Samsung CL32B226KAJNNNE 22 µF/25 V/X7R/1210 from post-shunt SYS_5V to GND.
  • Removed 3 × 1800 µF bulk and installed Panasonic EEH-ZC1E101XV 100 µF/25 V polymer on SYS_5V.
Branch map
  • U4 coordinator branch: SYS_5V -> COORD_5V -> X1 VBUS; provisional RILM 3.83 kΩ, about 0.87 A nominal. Cold-start measurement is required.
  • U5 bank A: SYS_5V -> SCAN_A_5V -> U16-U18 VBUS.
  • U6 bank B: SYS_5V -> SCAN_B_5V -> U19-U21 VBUS.
  • U7 bank C: SYS_5V -> SCAN_C_5V -> U22-U24 VBUS.
  • Scanner RILM is exact RC0603FR-072K49L 2.49 kΩ ±1%, nominal about 1.34 A; documented engineering range 1.19-1.49 A.
  • PG statuses are COORD_PG, SCAN_A_PG, SCAN_B_PG and SCAN_C_PG. Command interfaces are SCAN_A_CMD/B_CMD/C_CMD. Branch EN pulldowns enforce default-off.
Hardware validity logic
  • TPS3808G01DRVT monitors SYS_5V through 110 kΩ/10 kΩ and CT=10 nF; released status is SYS_5V_VALID. Exact threshold/delay corner proof remains open.
  • SN74LVC1G74 implements POWER_FAULT_LATCH. TPS3808 assertion asynchronously presets the fault state; active-low PDO contract decode and requalification logic use SN74LVC gates.
  • Implemented named equations: U3_ENABLE derives from STUSB-authorized U2 enable, USB_INPUT_VALID, and NOT_POWER_FAULT_LATCH. POWER_VALID derives from FULL_PD_VALID, USB_INPUT_VALID, SYS_5V_VALID, and NOT_POWER_FAULT_LATCH. No firmware override is provided.
Remaining blockers / gates
  • U2 production OVLO/UVLO/PGTH/dVdt/ITIMER network and exact 3.2 A RILM conversion were not completed; existing U2 RILM remains 665 Ω (~5 A). This blocks approval.
  • Branch OVLO/dVdt/ITIMER were left intentionally NC/fastest rather than falsely claiming calculated production values; exact startup-transient and latch timing networks remain required. This blocks approval.
  • Logic IC local 100 nF decoupling was not completed. POWER_OK2/3 pull-up electrical contract needs final ST datasheet confirmation.
  • TPS3808 threshold and CT full-tolerance proof, fail-latch power-up truth-table proof, and stable attach/PDO clear timing require completion.
  • Schematic placement/SLC cleanup remains; components were electrically inserted but not fully arranged.
  • Bench gates: STUSB NVM programming/readback, Samsung-model/PSpice compensation validation, XIAO coordinator and three-module bank cold-start/inrush measurements, branch latch reset on detach/requalification.
Status
JOB 1B PARTIAL / CAPACITY CHECKPOINT — overall Job 1B is not complete. The LTC4416 source-selector block is implemented and directly verified; scanner banks, logic/load shed, charger gate, U2/U7 production support, test points, and geometry cleanup remain. Schematic-only changes were made. No PCB layout, placement, routing, board outline, connector location, XIAO GPIO assignment, RF block, or manufacturing-file mutation was performed.
Checkpoint time: 2026-07-24T00:39Z.
Completed items
U3 feedback-only update
  • Replaced generic R24 with Yageo RT0603BRD0732KL, 32.0 kΩ ±0.1%, R0603.
  • Replaced generic R25 with Yageo RT0603BRE0710KL, 10.0 kΩ ±0.1%, R0603.
  • Connectivity verified: USB_5V -> R24 -> U3_FB -> R25 -> GND; U3 FB remains post-shunt.
  • Static target recorded: 4.982 / 5.040 / 5.098 V.
  • Focused ERC at 2026-07-24T00:25:22Z: no R24-matched floating/missing-power/NC/pin/short/driver/single-pin/undriven/unconnected-endpoint findings.
U8 feedback, compensation, capacitor bank and enable
  • R10: Yageo RT0603BRD0775KL, 75.0 kΩ ±0.1%, R0603.
  • R11: Yageo RT0603BRE0710KL, 10.0 kΩ ±0.1%, R0603.
  • R12: Yageo RT0603BRD0725K5L, 25.5 kΩ ±0.1%, R0603.
  • C61: Murata GRM1885C1H392JA01D, 3.9 nF ±5%, 50 V C0G, C0603.
  • Compensation connectivity: U8 COMP -> R12 -> U8_COMP_RC -> C61 -> GND. Loop stability/transient performance remains simulation- and bench-required; ERC does not prove stability.
  • Input bank: C10/C62/C63/C64 = 4 × Taiyo Yuden MCASE32MAB5476KPNDT1, 47 µF 16 V X5R 1210; C65 = KEMET C0603C104K4RACTU 100 nF HF bypass. All connect BAT_BOOST_IN-to-GND.
  • Output bank: C11/C12/C13/C66 = 4 × MCASE32MAB5476KPNDT1, BAT_5V-to-GND.
  • C31 = TDK CGA3E1X7R1C105KT0Y0N, 1 µF 16 V X7R, VCC-to-GND.
  • C17 = KEMET C0603C104K4RACTU, 100 nF, connected strictly BST-to-SW (not ground).
  • U8 EN intentionally connected to BAT_BOOST_IN for safe battery-capable operation when protected input exists; no floating EN.
  • Static target recorded: 4.989 / 5.100 / 5.211 V.
  • Focused ERC at 2026-07-24T00:25:13Z: no U8-matched requested electrical findings.
SYS_5V bulk
  • Added C67/C68/C69 = 3 × Nichicon PCG0J182MCL1GS, 1800 µF 6.3 V polymer SMD can, positive pin 1 to SYS_5V and pin 2 to GND.
  • Metadata records nominal 5400 µF, minimum 4320 µF, effective parallel ESR about 4.7 mΩ, source-handoff bulk.
  • Focused ERC at 2026-07-24T00:25:29Z: no C67-matched requested electrical findings.
Coordinator and XIAO grounds
  • X1 VBUS connected directly to SYS_5V (always-on coordinator).
  • X1 and U16-U24 GND pins connected to GND.
  • Existing XIAO GPIO signal assignments were not altered.
Fan provisional state
  • CN1 metadata explicitly states: FAN BRANCH PROVISIONAL - ACP2006 MAX VOLTAGE/START/STALL UNQUALIFIED; do not power from raised SYS_5V.
  • CN1 was not connected to raised SYS_5V.
Unattempted / remaining exact actions
  1. COMPLETED: Replaced U4/U9 and obsolete R2/R4/C2/C4/C6/C8 with U25 LTC4416IMS#TRPBF, Q5/Q6 CSD25402Q3A, exact threshold/bypass/status network; eliminated populated Net 1 membership and restored U6 VBUS to USB_5V.
  2. Add DNP CP footprint for U8 and requested test points.
  3. Add three TPS22990 scanner banks and rewire U16-U24 VBUS by bank.
  4. Add SN74LVC1G32 plus three SN74LVC1G08 load-shed logic gates, U13 command allocation, defaults, and decoupling.
  5. Add charger-enable SN74LVC1G08 + 2N7002Q-7-F gate.
  6. Complete U2/U7 production support networks and tolerance calculations.
  7. Add all requested manufacturer-backed test points.
  8. Arrange modified schematic blocks and resolve local SLC geometry warnings.
  9. Run all remaining focused ERC/SLC block loops.
Blockers / cautions
  • The approved implementation is too large to complete safely in this execution window; no claim of overall completion is made.
  • U2/U7 support values still require current-datasheet threshold, inrush and ITIMER calculations before mutation.
  • U8 CP remains unimplemented; simulation and bench validation remain mandatory.
  • U4/U9 have been removed and replaced by the implemented U25/Q5/Q6 LTC4416 source-selector stage. The remaining architecture is incomplete because scanner-bank load shedding, charger gating, U2/U7 support, test points, and local geometry cleanup are not yet implemented.
  • Local schematic geometry checks reported wire/symbol and label collisions after automatic insertion. Electrical focused checks above were clean, but SLC cleanup remains.
Next exact action
Proceed with scanner power banks and hardware load shed: add three TPS22990DMLR, verify current TI pin/application data externally (the Flux part has no attached datasheet), then add the OR/AND logic, U13 P00-P04 command nets, defaults, and decoupling.
Job 1B source-selector implementation (2026-07-24)
  • Removed U4/U9 TPS259474LRPWR and obsolete direct support R2/R4/C2/C4/C6/C8 after snapshotting their nets.
  • Added U25 Analog Devices LTC4416IMS#TRPBF, MSOP-10; Q5/Q6 TI CSD25402Q3A, VSONP-8; R46 Yageo RC0603FR-0773K2L 73.2 kΩ; R47 RC0603FR-0724K9L 24.9 kΩ; R48 RC0603FR-07909KL 909 kΩ; R49 AC0603FR-07100KL 100 kΩ; C70-C72 KEMET C0603C104K4RACTU 100 nF.
  • U25 V1/E1 and Q5 drains connect USB_5V; U25 V2 and Q6 drains connect BAT_5V; U25 VS and both PFET source banks connect SYS_5V. This places each P-channel intrinsic diode from the input-side drain toward the SYS-side source, allowing input-to-SYS startup conduction while blocking SYS-to-input. Upstream U2/U7 remain the full-disconnect elements.
  • U25 G1 drives Q5 gate; G2 drives Q6 gate. H1 is intentionally unused/NC because the datasheet defines it as an optional open-drain comparator/hysteresis output. U25 GND is grounded.
  • E2 network is exactly USB_5V -> R46 73.2 kΩ -> USB_PRIORITY_E2, with R47 24.9 kΩ to GND and R48 909 kΩ to H2. H2 is USB_PRIMARY_VALID, pulled to PERIPH_3V3 by R49 100 kΩ; it is high when USB is valid.
  • C70, C71, C72 bypass V1/USB_5V, V2/BAT_5V, and VS/SYS_5V respectively to GND.
  • U6 BQ25895 VBUS now directly belongs to USB_5V. Direct inspection showed no populated Net 1, USB_OR_, or BAT_OR_ source-selector memberships remaining.
  • Threshold calculations using VREF=1.180/1.215/1.240 V and all 1% resistor corners: nominal fail 4.7868 V, nominal restore 4.8846 V; fail worst-case 4.5802-4.9589 V; restore worst-case 4.6734-5.0608 V. These static corners neglect H2 VOL/leakage and E2 leakage; bench characterization remains required.
  • Focused direct inspection and ERC at 2026-07-24T00:39Z found no Q5- or USB_PRIMARY_VALID-matched floating, NC, short, pin, power, single-pin, undriven, or endpoint findings. Direct net inspection verified all duplicate Q5/Q6 drain/source package pins and U6 VBUS memberships.
  • Remaining bench requirements: source switchover/dropout, reverse-current blocking, PFET thermal rise at peak load, threshold hysteresis including leakage/VOL, and SYS_5V transient behavior with the installed polymer bank.
ACU
Remaining ACU count is unavailable from project tools.
Job 1D precision USB fail/restore supervisor qualification — BLOCKED / no schematic mutation
Qualification date: 2026-07-24. Scope was limited to the existing U25 LTC4416IMS#TRPBF, Q5/Q6 CSD25402Q3A source selector and a possible precision USB-valid supervisor. Scanner banks, charger gating, PCB/layout, connectors, GPIO, RF, board outline and unrelated circuitry were not touched.
Live-state findings
  • U3 approved static output bound was verified from the live Job 1 records and installed 0.1% divider: 4.982 V minimum, 5.040 V nominal, 5.098 V maximum.
  • Q5 USB PFET is CSD25402Q3A; the prior conservative hot design resistance is 13.35 mΩ, producing 66.75 mV drop at 5 A.
  • SYS_5V bulk is C67-C69, 3 x PCG0J182MCL1GS: 4320 µF minimum and approximately 4.7 mΩ parallel ESR.
  • U25 wiring was directly re-read: V1/E1 and Q5 drains are USB_5V; V2 and Q6 drains are BAT_5V; VS and both PFET source banks are SYS_5V; G1/G2 drive Q5/Q6. The unsafe priority network remains USB_5V -> R46 73.2k -> USB_PRIORITY_E2, R47 24.9k to GND, R48 909k to U25 H2, and R49 100k from PERIPH_3V3 to H2/USB_PRIMARY_VALID.
  • ADI specifies U25 E comparator reference 1.180-1.240 V, E leakage ±100 nA, H output leakage ±1 µA, H low 100 mV max, H turn-on 5 µs, H turn-off 10 µs. The existing H2 pull-up is therefore part of the hysteresis network and changes its thresholds; the recorded worst-case fail/restore ranges (4.5802-4.9589 V / 4.6734-5.0608 V) are unsafe. U25 remains suitable as the ideal-diode/PFET controller, but its internal E2/H2 comparator is not suitable for this narrow USB-valid window.
Candidate comparison
  • Lead candidate: TI TPS3700DDCR2, production-orderable Flux part be828488-d603-402a-aca4-c4042a36ab53, SOT/TSOT-23-6. TI guarantees a 400 mV threshold at 396-404 mV (±1%) over -40 to 125 C, open-drain outputs, 18 µs maximum assertion delay and 29 µs maximum release delay at 10 mV overdrive, 1.8-18 V supply, 450 µs maximum startup-valid time, and internal hysteresis 5.5 mV typical / 12 mV maximum.
  • Precision alternative: ADI LTC2964 family, ±ADJ threshold 497.5-502.5 mV (±0.5%) over temperature, real-time open-drain OUT pins, and 40 µs maximum invalid propagation at 10% overdrive. It is materially more complex than required and its anti-glitch filtering does not provide a separately guaranteed narrow fail/restore hysteresis window.
  • TPS3899 was also checked but rejected as a precision adjustable alternative: its adjustable threshold is only ±2.5% maximum over temperature and its minimum sense delay has no listed maximum in the open-CTS condition.
Mandatory worst-case proof gate
Even before ripple or collapse-delay droop, the minimum USB sensing-point voltage needed to hold the distant load above 4.80 V using the project’s existing conservative allowances is:
4.800 V + (5 A x 13.35 mOhm) + 20 mV trace/selector allowance = 4.88675 V.
This leaves only 95.25 mV below U3’s guaranteed static minimum of 4.982 V for supervisor tolerance, guaranteed hysteresis, ripple, contact/trace uncertainty beyond the provisional 20 mV, propagation delay, source collapse slew and source-selector transition.
TPS3700 cannot guarantee a non-overlapping fail/restore window even under the optimistic zero-ripple/zero-delay case. Combining its ±1% threshold with 0.1% divider resistors, a falling threshold guaranteed no lower than 4.88675 V can range as high as approximately 4.99545 V. A restore threshold guaranteed no higher than 4.982 V can range as low as approximately 4.87359 V. These independent full-tolerance intervals overlap/invert, before input-current error and before assigning ripple/noise margin. Therefore no divider or external hysteresis network using TPS3700 proves both early failover and guaranteed restore without chatter.
The tighter LTC2964 threshold still cannot close the system requirement from current records because the following required quantities are not bounded: U3 worst-case ripple/load-transient droop at 5 A; actual USB collapse slew/shape; final sensing-point-to-Q5 and Q5-to-most-distant-XIAO power/return/contact resistance; U8 loaded transient minimum and takeover waveform; and source-selector transition behavior with the installed bulk. Existing records explicitly leave U3/U8 loop/transient validation pending. With no bound on ripple or collapse rate, propagation-delay droop cannot be bounded, so the required 4.80 V minimum cannot be mathematically proven for any supervisor topology.
Decision and blocker
Per the Job 1D stop rule, no schematic components, nets, passives, test points or properties were added, removed or rewired. The unsafe LTC4416 threshold/H2 network was not revised because no replacement topology passed the complete proof gate; partially disconnecting it would leave source priority undefined. No ERC/SLC run was required because there was no schematic mutation.
Exact unblock evidence: validated worst-case U3 ripple/transient bound at 5 A and temperature; measured or specified USB collapse slew envelope; finalized distribution/contact resistance to the most distant XIAO; validated U8 loaded minimum/takeover transient; and a guaranteed supervisor fail/restore design whose full tolerance plus timing fits between the resulting fail floor and 4.982 V restore ceiling. Bench tests must then cover slow collapse/recovery, ripple injection, hot/cold thresholds, USB insertion/removal, no-source power-up, battery-only power-up, valid-USB recovery, reverse leakage/cross-conduction, and distant-XIAO VBUS minimum.
Approval status: not approval-ready for scanner-bank/load-shed work. The precision USB-valid/failover control remains blocked by missing system dynamic bounds and the existing H2-loaded LTC4416 network remains unsafe.
Job 1E system-boundary characterization — COMPLETE / ARCHITECTURE REDESIGN REQUIRED
Characterization date: 2026-07-24. This was a read-only schematic task plus calculations and behavioral simulation. No schematic, PCB, connector, GPIO, RF, outline, placement, routing or manufacturing data was modified.
Disposition
The Job 1D precision-supervisor window remains not production-provable. The additional work did not show that a particular supervisor is unsafe; it established that the current source-selection requirements cannot be guaranteed with the present converter, load-shed and component-timing evidence. The threshold window is empty once documented ripple allowance and production timing requirements are included.
Evidence classification
  • Documented manufacturer limits: directly stated in manufacturer datasheets.
  • Calculated limits: arithmetic from documented component values and explicit project assumptions.
  • Behavioral simulation: source/capacitor/load boundary models; not encrypted TI transistor/controller models.
  • Unbounded: no manufacturer maximum, no exact production part, or no verified system measurement/model.
Manufacturer-documented boundaries
U3 TPS552882 USB converter
  • Installed 0.1% feedback gives 4.982 / 5.040 / 5.098 V static minimum/nominal/maximum.
  • FB reference: 1.188–1.212 V over the TI electrical-characteristic conditions.
  • Soft start: 3–5 ms.
  • Installed output shunt: 10 mΩ ±1%. TI current-loop sense threshold is 48–52 mV, giving a calculated guaranteed output-current-limit range of 4.752–5.253 A. Therefore the schematic does not guarantee a full 5.000 A before current-limit action; the 4.61 A engineering peak has only about 0.14 A margin to the worst current-limit corner.
  • TI's 5 V reference design states a ±50 mV output-ripple design requirement, not a guaranteed achieved maximum for this board.
  • TI provides a 2.5-to-5 A load-transient plot, but no numeric guaranteed droop/overshoot limit. The live C44-C47 output bank remains four generic 22 µF/16 V/X7R/1210 entries without exact production MPNs or DC-bias/ESR curves. U3 ripple, load-step droop, overshoot and recovery therefore remain unbounded.
  • PG is high impedance above 95% of target and low below 90%; TI does not specify an explicit PG propagation/deglitch maximum. PG is too late to directly protect a 4.80 V load floor by itself.
TI source: https://www.ti.com/lit/ds/symlink/tps552882.pdf
U8 TPS61288 battery converter
  • Installed 0.1% feedback gives 4.989 / 5.100 / 5.211 V static minimum/nominal/maximum.
  • FB reference: 0.588–0.612 V.
  • Peak switch-current limit: 12 A minimum, 15 A typical, 17.1 A maximum under the stated TI test condition.
  • Soft start is about 3 ms typical only under a different 16 V application condition.
  • Battery power ceiling from the approved 3.0 V, 5 A input and 88% assumption is 2.64 A at 5.0 V, or 2.588 A at 5.1 V. This is below the 4.61 A engineering USB peak.
  • The four exact 47 µF MCASE32MAB5476KPNDT1 output capacitors have graph-only DC-bias and ESR data. The prior approximately 28 µF-per-part reading at 5.1 V is not a tabulated manufacturer guarantee. No aging value is published in the retrieved specification. Exact effective COUT remains a validation item.
  • TI provides no numeric guaranteed load regulation or transient droop for 3.0 V to 5.1 V at 2.64 A. The official PSpice model exists but is encrypted/targeted to PSpice for TI and was not executable in the available project simulator. U8 takeover waveform and recovery remain unbounded.
TI source: https://www.ti.com/lit/ds/symlink/tps61288.pdf
Taiyo Yuden source: https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/5485/MCASE32MAB5476KPNDT1_SS.pdf
U25 LTC4416 and Q5/Q6
  • LTC4416 forward regulation: 40 mV maximum; reverse turn-off threshold: −40 to −10 mV; fast-on threshold: 50–125 mV under its stated test range.
  • Gate turn-on test: 60 µs to VGS Q6 -> SYS_5V`, controlled by U25 G2. It was not removed because the approved replacement bypass could not be instantiated; removing it alone would create a partially implemented battery architecture.
  • Existing battery-input chain remains BAT_RAW -> F1 0451010.MRL -> BAT_FUSED -> U5 LTC4365/Q1 FS8205A -> BAT_PROTECTED -> U7 TPS259474LRPWR -> BAT_BOOST_IN.
Hard library blockers
Mandatory exact-part keyword and constrained agentic searches confirmed these approved parts are not in the Flux library:
  • Littelfuse 0451015.MRL 15 A fuse. The only lexical hit was 045101.5MRL, a 1.5 A part; it was explicitly rejected as unsafe.
  • Analog Devices LTC4373HDD#TRPBF. Flux contains LTC4373IMS8#PBF, but not the required H-temperature DFN variant; no package/grade substitution was made.
  • Vishay SQJ128ELP-T1_GE3. No exact library part was found; other SQJ MOSFETs were rejected as unapproved substitutions.
  • Texas Instruments TPS259830ONRGER. Flux returned TPS259803ONRGER and TPS25982-family parts, not the requested exact MPN; no substitution was made.
Missing-part requests were submitted for all four exact MPNs. Because these parts form the upstream protection, high-current limiter and main bypass safety chain, partial rewiring would defeat direct inspection and fail-safe review. Therefore no power-path or XIAO VBUS net mutation was performed.
Timer/source findings
  • Exact active LTC6994HS6-1#TRPBF is present in Flux (H grade, TSOT-23-6), so the >=1 ms delayed-rising-valid timer itself is not the blocker.
  • Datasheet extraction verified pins IN, GND, SET, DIV, V+, OUT; DIVCODE 3 uses NDIV=512 with R1=1.00 MOhm and R2=280 kOhm; RSET=101 kOhm gives 1.034 ms nominal. With 1% RSET and the datasheet's full-temperature +/-3.0% delay error for NDIV>=512, the simple stacked lower bound is about 0.993 ms, not >=1.0 ms. This approved value therefore requires tolerance interpretation/adjustment before claiming the stated guaranteed >=1.0 ms requirement.
  • The timer was intentionally not added as an orphan block. BYPASS_QUALIFIED remains impossible to newly assert because the Job 1G qualification/bypass chain was not created.
  • No exact verified 25 ms timeout implementation was selected. The required open item remains: PRECHARGE_TIMEOUT_25MS_REQUIRED; it must be fault-only and must never command bypass closure.
Power/fault state table (required behavior; not yet implemented)

Table

StatePrechargeBypassX1Scanner banks
Battery/U8 invalid, brownout, missing logic power, emergency shutdown, or any upstream/eFuse/precharge faultOFFOFFOFFOFF
BAT_5V valid and no fault; SYS not yet matchedONOFFOFFOFF
SYS approximately BAT continuously through qualified >=1 ms timer and no faultOFF after bypass closesONeligible after bypass stabilityOFF until gated commands
Bypass qualification lost or any fault assertedasynchronously OFFasynchronously OFFOFFOFF
USB-only valid operationbattery precharge/bypass OFFbattery bypass OFFexisting USB behavior preservedexisting behavior preserved until Job 1G switches exist
Cost/area/thermal impact status
  • Not finalized because the four mandatory exact parts cannot be instantiated or priced from the Flux BOM.
  • Expected architecture impact remains two LTC4373 controllers, four SQJ128 MOSFETs, one TPS259830 eFuse, one TPS259474 precharge eFuse, one TLV9024 quad comparator, one TLV431B-class reference, one LTC6994 timer, four TPS22990 load switches, logic/gating devices and support passives.
  • Dominant thermal validations remain TPS259830 at 8.906 A operating requirement, both back-to-back SQJ128 pairs at full current, TPS259474 precharge SOA into nominal 5.4 mF, and each load switch at module-bank peak current.
Required simulation and bench tests
  • PSpice/transient: upstream protection startup/reverse event, TPS259830 current-limit tolerance and latch-off, U8 startup into isolated precharge, TPS259474 precharge into 4.32-5.4 mF with 25 ms timeout, bypass overlap/turnoff, and complete fault-dominant asynchronous chain.
  • Bench: 3.0 V full-power boundary, 2.5 V shutdown/brownout behavior, fuse/eFuse coordination, reverse battery/output, pack/BMS OV behavior and PACK_ID, precharge current and capacitor charge time, SYS-vs-BAT Kelvin mismatch threshold, >=1 ms continuous qualification, timeout incapable of closing bypass, every fault injection, missing-logic-power default-off, X1 then staged bank sequencing, and hot thermal rise at sustained/peak load.
Approval status
Job 1G implementation is failed/blocked, not partially approved. The live schematic remains at the pre-Job-1G architecture. It is not ready for the requested user approval checkpoint and is not production-approved. Unblock by adding/verifying the four exact library parts (or obtaining explicit approval for exact alternate package/MPNs), then re-run datasheet-backed design, mutation, direct pin/net inspection and focused ERC/SLC.

  • HellzGate V2 Job 3G1 — Molex microSD replacement and south service-edge placement (2026-07-27)

  • HellzGate V2 Job 3D — controlled placement-feasibility pass (2026-07-27)

  • Foundation verification

  • Enforced analysis constraints

  • Provisional placement attempt and inspection

  • Required dimensional or architectural change

  • Revert and mutation audit

  • HellzGate V2 Job 3C — PCB foundation checkpoint (2026-07-26)

  • HellzGate V2 Job 2F1 — GNSS RF schematic implementation (2026-07-26)

  • Private exact bias component

  • Implemented RF block

  • Net map

  • Default population

  • Interface record

  • Verification and BOM

  • Approval gates

  • HellzGate V2 Job 2D1 — Final schematic cleanup and GPS closure (2026-07-26)

  • Removed components

  • ATGM336H-5N31 digital/control disposition

  • GPS RF research and decision

  • Final ERC

  • Remaining gates

  • HellzGate V2 Job 2D — Schematic blocker closure (2026-07-26)

  • CP2102N U14

  • TCA9548A U11/U12

  • ERC disposition

  • Whole-schematic ERC

  • Evidence required and qualification gates

  • V2 Job 2C — Complete schematic approval review (2026-07-26)

  • Authorized correction

  • Architecture audit

  • Whole-schematic ERC

  • Placement unblock requirements

  • Firmware review items

  • V2 Job 2B1 — Existing U13 scanner-command completion (2026-07-26)

  • Final narrow Job 2B coordinator/GPS correction (2026-07-26)

  • Focused Job 2B completion pass (2026-07-26)

  • V2 Job 2B direct-PD schematic execution (2026-07-26)

  • Architecture and power flow

  • U3 and SYS values

  • Branch map

  • Hardware validity logic

  • Remaining blockers / gates

  • Status

  • Completed items

  • U3 feedback-only update

  • U8 feedback, compensation, capacitor bank and enable

  • SYS_5V bulk

  • Coordinator and XIAO grounds

  • Fan provisional state

  • Unattempted / remaining exact actions

  • Blockers / cautions

  • Next exact action

  • Job 1B source-selector implementation (2026-07-24)

  • ACU

  • Job 1D precision USB fail/restore supervisor qualification — BLOCKED / no schematic mutation

  • Live-state findings

  • Candidate comparison

  • Mandatory worst-case proof gate

  • Decision and blocker

  • Job 1E system-boundary characterization — COMPLETE / ARCHITECTURE REDESIGN REQUIRED

  • Disposition

  • Evidence classification

  • Manufacturer-documented boundaries

  • Load and minimum-voltage boundary

  • Calculated steady-state distant-XIAO voltages

  • Behavioral failover simulation results

  • Load-shed timing boundary

  • Repeated Job 1D supervisor-window proof

  • Smallest recommended deterministic architecture change — do not implement yet

  • Remaining mandatory evidence

  • Approval status

  • Job 1G full-power/precharge implementation attempt — BLOCKED / FAIL-SAFE STOP

  • Direct live-state inspection

  • Hard library blockers

  • Timer/source findings

  • Power/fault state table (required behavior; not yet implemented)

  • Cost/area/thermal impact status

  • Required simulation and bench tests

  • Approval status

HellzGateC5 v2

HellzGateC5 v2 thumbnail
Production-readiness engineering review of the ESP32-C5 Node Cluster V2 EasyEDA design, including schematic, PCB, Gerbers, BOM, pick-and-place, power, RF, and battery safety.

Properties

Properties describe core aspects of the project.

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