Schematic Completion Pass 2 Capacity Checkpoint
Stop reason
Execution capacity ended before the focused schematic-completion pass could finish. This checkpoint records the exact post-mutation state. Resume from the current live schematic; do not restart, rebuild, delete prior work, touch PCB layout, or create manufacturing files.
Status at stop
- Production status: STOP-SHIP.
- Schematic status: partial; not ready for independent review.
- Fresh exhaustive review timestamp: 2026-07-23T21:12:18.029Z.
- Unresolved schematic findings: 316 errors.
- Floating Pin: 300 errors.
- Missing Power: 16 errors.
- No unresolved ERC item has been waived.
- No PCB/layout/manufacturing mutation was made.
Mutations completed in this pass
- Verified from the TI TPS25947 datasheet that TPS259474 includes integrated back-to-back MOSFETs and blocks reverse current from OUT to IN; U4 and U9 remain suitable for the intended 5 V source-isolation/ORing role, subject to completing their support/control networks.
- Verified the TI TPS552882 9–20 V to 5 V / 5 A reference operating point: 4.7 µH power inductor, 10 mΩ output-current sense, 400 kHz switching, and external buck-side N-channel MOSFETs.
- Added two real Flux-library-supported Texas Instruments CSD17578Q5A MOSFETs:
- Q2: U3 buck high-side FET.
- Q3: U3 buck low-side FET.
- Verified library metadata: 30 V, 25 A class, 6.9 mΩ, 7.9 nC, TDSON-8-1.
- Created and wired
U3_SW1:
- Q2 source pins 1/2/3.
- Q3 drain.
- U3 SW1 pin 23.
- L1 pin 1.
- Connected Q2 drain to
VBUS_PROTECTED.
- Created and wired
U3_DR1H_GATE: U3 DR1H pin 2 to Q2 gate.
- Created and wired
U3_DR1L_GATE: U3 DR1L pin 1 to Q3 gate.
- Connected Q3 source pins 1/2/3, U3 PGND pins 9/24, and U3 AGND pin 10 to GND.
- Created and wired
U3_SW2: L1 pin 2 to both U3 SW2 pins 21/25.
- Preserved existing L1 as exact Coilcraft XAL1010-472MED, 4.7 µH.
- The pass reduced unresolved findings from 326 to 316 and removed the earlier U3 power-stage/L1/Q2/Q3 floating-pin findings.
Verified current U3 connectivity
VBUS_PROTECTED: U2 OUT, U3 VIN, Q2 drain.U3_SW1: Q2 sources, Q3 drain, U3 SW1, L1 P1.U3_SW2: L1 P2, U3 SW2 pins 21 and 25.U3_DR1H_GATE: U3 DR1H to Q2 gate.U3_DR1L_GATE: U3 DR1L to Q3 gate.- GND: U3 PGND pins 9/24, U3 AGND pin 10, Q3 sources.
- Existing
USB_5V: U3 VOUT pin 11, U4 IN/EN, U6 VBUS. U3 VOUT pin 26 still requires connection during the remaining U3 network completion.
Current U3-scoped ERC
Fresh U3-scoped review timestamp: 2026-07-23T21:11:34.224Z.
Floating Pin — 16
- U3 CC_N
- U3 MODE
- U3 FB
- U3 COMP
- U3 VCC
- U3 VOUT pin 26
- U3 FSW
- U3 ISN
- U3 ILIM
- U3 EN
- U3 BOOT1
- U3 PG
- U3 CDC
- U3 BOOT2
- U3 DITH_SYNC
- U3 ISP
Missing Power — 1
Full current ERC grouping
Missing Power — 16
- U17 VBUS
- U18 VBUS
- U23 VBUS
- U15 VBAT
- U3 VCC
- U16 VBUS
- U24 VBUS
- U21 VBUS
- U20 VBUS
- U1 VBUS_EN_SNK
- D1 VBUS
- U14 VDD
- U14 VBUS
- U22 VBUS
- U10 VCC
- U19 VBUS
Floating-pin work remains concentrated in
- U3 TPS552882 remaining support network.
- U10 LMR33630 support network.
- U1 STUSB4500 controls/status/address/discharge.
- U2/U4/U7/U9 TPS259474 OVLO/PGTH support.
- U16–U24 scanner XIAO power, I2C, intended GPIO, and unused-pin NC assignment.
- U11/U12 I2C switches, U13 GPIO expander, U14 USB-UART, U15 GPS, J3 microSD, CN1 fan, D1 USB protection, X1 coordinator.
- Unwired existing passives including C14–C28, C32/C33, L4, R8, R13–R15 and related block support parts.
Next exact action
Continue mandatory step 2 and finish U3 TPS552882 using the verified TI reference values and calculations:
- 10 mΩ current-sense resistor between ISP/ISN in the correct output-sense position.
- 4 × 10 µF input capacitors.
- 4 × 22 µF output capacitors with effective-capacitance/voltage validation.
- 4.7 µF VCC capacitor.
- 100 nF BOOT1-to-SW1 and 100 nF BOOT2-to-SW2 capacitors.
- 49.9 kΩ FSW resistor for 400 kHz.
- 19.9 kΩ ILIM resistor.
- 29.4 kΩ MODE resistor.
- 100 kΩ CDC resistor/network.
- 150 kΩ / 6.19 kΩ FB divider for the exact reference output setpoint, with both U3 VOUT pins connected correctly.
- Exact TI compensation network for this 4.7 µH / output-capacitance / 5 A operating point.
- EN/UVLO from the validated USB/PD path.
- PG pull-up and intended status destination.
- Datasheet-defined DITH/SYNC and CC_N states.
- Assign verified packages, voltage/current/power ratings, Role and Role Details to all new support components.
- Run U3-scoped ERC and correct it to zero before proceeding to U10.
Remaining mandatory order after U3
- Complete U10 LMR33630.
- Complete STUSB4500 control/reset/discharge/status/PD circuitry.
- Complete all TPS259474 support networks and source controls.
- Complete TPS61288 compensation and USB-valid shutdown/recovery handoff.
- Complete PACK_ID, PACK_NTC, fan, scanner-node and peripheral wiring.
- Assign verified packages/footprints to every component.
- Clean schematic geometry and clear all 316 current/new ERC findings to zero.
- Produce the power-state table and USB/battery budgets, then confirm independent-review readiness.
Approval gate
Do not begin PCB layout or create manufacturing files until the owner approves the completed schematic.