Job 3G1 Correction
Thought for 35 sec
Thought for 11 sec — Inspecting project components
Reading layout details of LTC4373HDD#TRPBF.
Looking at the board of LTC4373HDD#TRPBF.
Reading symbol pins.
Thought for a moment
Analyzing pin layout issues
I see that there are problems with the EP terminal, which was generated as a perimeter pin, and the thermal pad being unbound. The project is HellzGate, but I can't mutate external components. I wonder if I can fix it by checking the part layout or submitting a quality issue. The pin placement seems incorrect too: the left row should have pins ordered as OUT 1, GATE 2, SOURCE 3, IN 4, while the right row has issues with UV and EP placements as well. This definitely needs attention!
Addressing thermal pad issue
Oh no, the thermal pad is separate and
there are two pads "IN_5" and "GND_4" which look like they should simply be GND
Thought for 11 sec
Those pads indicate the TPS259830ONRGER, not the LTC4373. They must not both be GND:
IN_5/ Thermal Pad 1 → INGND_4/ Thermal Pad 2 → GND
TI specifies two electrically distinct exposed pads; shorting both to GND would directly short the input rail. The footprint naming may be awkward, but that separation is electrically required.
Audit both footprints
Fix LTC4373 part
Inspect TPS259830 part
Remove bad LTC4373
Create repair plan
Refine this doc
Ask about this doc
ESP32-C5 Node Cluster V2 — Production Readiness Review
Review date: 2026-07-23
Source package: EasyEDA Pro
Disposition: STOP-SHIP — do not order this revision.
Source package: EasyEDA Pro
.epro2, 3-page schematic PDF, 2-layer Gerbers, Excellon drills, BOM, pick-and-place, STEP, flying-probe data, and preview images.Disposition: STOP-SHIP — do not order this revision.
Executive summary
The manufacturing package is parseable and internally consistent enough for a serious audit, but the design is not production-ready. The highest-risk problems are the battery/charger architecture, direct paralleling of regulator outputs, external powering of the XIAO ESP32-C5 modules through their
3V3_OUT pins, uncontrolled aggregate USB current, and firmware/pin-label mismatches around UART/SPI. The board can also physically accept three directly paralleled Li-ion packs without individual isolation or protection.The PCB itself is manufacturable in broad terms, but a 2-layer stackup provides weak return-path control for a dense board with ten radios, a GNSS RF input, long shared buses, charging, and a fan. The RF trace is not demonstrably 50 Ω, and thermal/current margins are not established.
Overall scores
Table
| Category | Score | Rationale |
|---|---|---|
| Electrical Design | 3/10 | Core blocks exist, but power-source interaction and module pin usage contain stop-ship risks. |
| Power Integrity | 2/10 | No complete current budget, unsafe source/regulator interactions, and questionable transient capacity for ten ESP32 modules. |
| RF Layout | 3/10 | Short GNSS route, but no defined 50 Ω geometry or stackup; ten nearby radios and fan/power circuitry raise interference risk. |
| Manufacturability | 6/10 | Gerbers/BOM/PnP are largely coherent; drill-file ambiguity, polarity verification, and missing design-rule evidence remain. |
| Reliability | 2/10 | Battery safety, backfeed, thermal, ESD, and connector-protection risks are unresolved. |
| Production Readiness | 2/10 | Multiple confirmed stop-ship issues require a schematic and PCB revision. |
Stop-ship findings
C1 — Three Li-ion battery connectors are directly paralleled
- Severity: Critical
- Affected:
CN2,CN3,CN4,$3N41,Q5,B+,U8 - Evidence: All three connector positive pins join
$3N41; all negative pins join GND. A single AO3401A path connects the common positive node toB+, which is also the TP4056 BAT node. - Why it matters: Packs at different voltages can exchange uncontrolled equalization current. A single-cell TP4056 does not provide per-pack isolation, balancing, or independent protection.
- Exact correction: Populate only one battery connector, or isolate every connector with individual fuse/current limiting and ideal-diode circuitry under a documented matched-cell parallel-pack architecture. For a normal product, use one protected 1S pack and one keyed connector.
C2 — TP4056 is used without a true power path/load-sharing function
- Severity: Critical
- Affected:
U8 BAT/B+,SW1,POWER_VDC,+5V - Evidence: TP4056 BAT connects directly to
B+; the system load is switched fromB+toPOWER_VDC. No separateSYSoutput or power-path IC exists. - Why it matters: System current is mixed with battery charge current, which can prevent correct termination and disturb charger behavior. The board can run while charging, so this is not a theoretical condition.
- Exact correction: Replace U8 with a 1-cell charger that includes power-path management and input-current limiting, then create separate
VBATandVSYSnets. Suitable architecture: USB-C VBUS → protected/input-limited charger →SYS; battery → chargerBAT; all board loads fromSYS.
C3 — Battery temperature and pack protection are absent
- Severity: Critical
- Affected:
U8 TEMP,CN2–CN4,B+ - Evidence: TP4056 TEMP is tied to GND. No pack NTC input, cell-protection IC, battery fuse, or clearly documented protected-pack requirement is present.
- Why it matters: Charging is not inhibited outside safe cell temperature. Board-level short-circuit, over-discharge, and over-current protection are not established.
- Exact correction: Require a protected 1S pack and add a battery fuse/PTC sized from the current budget. Route a 10 kΩ NTC from the pack to the charger temperature input, or choose a charger with JEITA-qualified NTC handling. Add reverse-polarity protection and explicit battery polarity silkscreen.
C4 — U5 and U10 LDO outputs are directly paralleled
- Severity: Critical
- Affected:
U5,U10,+3.3V,+5V,POWER_VDC - Evidence: Both regulator output pins connect to the same
+3.3Vnet. Their inputs come from different sources and both enable pins are pulled high. - Why it matters: The regulators can fight or backfeed whenever both sources are present. Standard LDOs are not automatically safe to parallel or reverse-bias.
- Exact correction: Remove the parallel outputs. Generate the peripheral 3.3 V rail from the charger/power-mux
SYSrail using one regulator. If two sources must be retained, combine sources before the regulator with a rated power mux/ideal-diode controller—not after two LDOs.
C5 — The XIAO ESP32-C5
3V3 pins are output rails but are driven by external LDOs- Severity: Critical
- Affected:
U3,U4,U6,U7,U9; railsESP_1-2throughESP_9-10; headersH3/H5/H7/H9/H11/H13/H15/H17/H19/H21 - Evidence: The official XIAO ESP32-C5 schematic names the exposed rail
+3V3_OUT. It is the output of the module’s onboard buck regulator through a TPS22916 load switch. This carrier drives each module’s 3V3 header pin from an external TP6217 LDO. - Why it matters: This back-powers the XIAO internal 3.3 V rail through an output/load-switch node for which no external-source ORing is shown. It can cause regulator contention, reverse current, partial powering, and unpredictable startup.
- Exact correction: Do not power the XIAO modules through
3V3_OUT. Power each XIAO only throughVBUS/5V(or through a power topology explicitly approved by Seeed). Remove U3/U4/U6/U7/U9 and disconnect theESP_x-yrails from XIAO 3V3 pins. Leave those pins as outputs or unconnected unless used to power a small, budgeted local load.
C6 — Aggregate USB-C current is uncontrolled and potentially far above default-source capability
- Severity: Critical
- Affected:
USB1,R9,R12,+5V,U8,D1–D10, fan and module rails - Evidence: USB-C has correct 5.1 kΩ Rd resistors but no CC current-level detection, PD controller, or board-level input-current limiter. R17 = 1.2 kΩ programs TP4056 near 1 A by common TP4056 data. The same VBUS can feed ten XIAO modules and the fan.
- Why it matters: Rd identifies a sink but does not grant an unconditional 3 A budget. Charger current plus ten radios and fan load can overload the source, cable, connector, or traces.
- Exact correction: Complete a worst-case power budget first. Add an eFuse/input current limiter after USB-C. Either reduce charge current to fit the guaranteed source budget or add USB-C current advertisement detection/PD sink control and enforce the negotiated limit. A practical architecture should prioritize system load and dynamically reduce charge current.
C7 — No USB VBUS fuse/eFuse or transient protection
- Severity: Critical
- Affected:
USB1 VBUS,+5V - Evidence: Connector VBUS goes directly to the board
+5Vnetwork. No fuse/eFuse, TVS, or dedicated input over-voltage/reverse protection is in the BOM. - Why it matters: A short or downstream fault can stress the cable/source. Connector transients can reach charger, regulators, modules, and fan switch.
- Exact correction: Add a USB-rated low-capacitance ESD/TVS solution, an eFuse/current-limited load switch with reverse-current blocking, and sufficient local bulk capacitance. Set the current limit from the approved USB-C operating mode.
C8 — XIAO UART/SPI net names and default pin functions do not match the official pinout
- Severity: Critical for firmware bring-up; Major electrically
- Affected:
D1/TX,D2/RX,D3/CS,D7/EN,D8/MISO,D9/SCLK,D10/MOSI - Evidence: Official XIAO mapping is D6=TX/GPIO11, D7=RX/GPIO12, D8=SCK/GPIO8, D9=MISO/GPIO9, D10=MOSI/GPIO10. The carrier uses D1 for GPS TX-side net, D2 for GPS RX-side net, D3 as SD CS, D7 as fan enable, D8 as SD MISO, and D9 as SD SCLK.
- Why it matters: ESP32 GPIO-matrix remapping may make some choices functional, but standard XIAO/Arduino defaults will not match the hardware. The SD clock and MISO labels are swapped relative to the official header, and D7 is an RX-labelled pin rather than module EN. Unmodified example firmware is likely to fail or inadvertently control the fan.
- Exact correction: Either reroute to the official defaults—GPS TX→D7/RX, GPS RX→D6/TX, SD SCK→D8, SD MISO→D9, SD MOSI→D10, CS→a documented free GPIO—or preserve custom routing but rename every net by actual function/GPIO and provide explicit firmware pin definitions. Move fan enable to an unambiguous free GPIO. Never label D7 as module EN; module EN is a separate reset net/test pad.
Major findings
M1 — XIAO power-mode control is implemented with discrete NPNs but remains unsafe
- Affected:
Q1–Q4,Q6,R10/R11/R15/R16/R21, U3/U4/U6/U7/U9 CE - Evidence: Each SS8050 base is driven from
+5Vthrough 1 kΩ and pulls a pair-LDO CE low when USB power is present. - Risk: The intent appears to be 5 V module power on USB and external 3.3 V injection on battery. The latter is invalid because the XIAO 3V3 pin is an output. The circuit also wastes base current and creates mode-transition uncertainty.
- Correction: Delete this scheme. Use one board power mux/charger
SYSrail and feed all XIAO VBUS pins from a properly sized 5 V rail. If battery is 1S, generate 5 V with a current-rated boost or buck-boost converter sized for all modules.
M2 — Existing module-pair LDOs do not have a demonstrated current or thermal margin
- Affected:
U3/U4/U6/U7/U9, TP6217C33M5G - Evidence: Each 800 mA SOT-23 LDO feeds two XIAO 3V3 pins. Espressif guidance recommends a supply capability around 600 mA or more for one ESP32-C5 device. Two devices can therefore require more transient capacity than one 800 mA regulator.
- Risk: Brownouts, Wi-Fi transmit resets, thermal shutdown, and excessive SOT-23 temperature rise.
- Correction: Remove these LDOs as required by C5. For any retained regulator, calculate worst-case load and
(VINmax−VOUT)×I, then provide at least 25–50% transient margin and validate temperature at maximum ambient.
M3 — USB data pins are isolated and not orientation-paired
- Affected:
USB1 A6/B6/A7/B7, isolated netsNET_20/21/23/24 - Evidence: Each Type-C USB2 data pad is on a one-pad net. Nominal
D+andD-nets have zero connected pins in flying-probe data. - Risk: USB data/programming through the carrier connector cannot work.
- Correction: If charge-only, explicitly mark all data pins NC and document it. If data is required, tie A6+B6 as D+, A7+B7 as D−, add ESD protection, and route to one selected USB device through a proper mux/hub if multiple modules need USB.
M4 — GNSS RF route is not demonstrably 50 Ω
- Affected:
RF1,L1,U2 RF_IN,$1N133,$1N129 - Evidence: Route is ~6.36 mm total at 0.20 mm width on a 2-layer board with no documented stackup, impedance rule, or coplanar clearance. RF1 is only ~8 mm from the fan connector and ~11 mm from the fan load switch.
- Risk: Antenna mismatch, sensitivity loss, and coupling from fan/power transients.
- Correction: Define the fab stackup and recalculate the line as 50 Ω microstrip or grounded coplanar waveguide. Add ground via stitching at RF1 and along the route, keep a solid ground reference, and isolate the GNSS RF area from fan and digital return currents. Validate the L1 active-antenna bias network against the ATGM336H reference design and add suitable RF ESD.
M5 — 2-layer stackup is poorly suited to this density and RF/current mix
- Affected: Entire PCB
- Evidence: Only top and bottom copper exist. Both are routed and poured; exported GND fill is fragmented. The board has ten ESP32 radios, GNSS RF, charging, fan current, long I2C, and SPI.
- Risk: Return-current detours, RF degradation, common-impedance coupling, EMI, and harder power distribution.
- Correction: Move to 4 layers: L1 signals/components, L2 uninterrupted GND, L3 power distribution, L4 secondary signals/GND. Keep RF and fast edges referenced to L2. If cost forces 2 layers, reserve most of the bottom for unbroken GND and reroute power/signals to avoid plane cuts.
- Affected:
SDA,SCL, H2/H4/H6/H8/H10/H12/H14/H16/H18/H20, R4/R5 - Evidence: SDA is ~245 mm of 0.2 mm routing and SCL ~227 mm, with all ten XIAO modules connected. One 4.7 kΩ pull-up pair serves the whole bus.
- Risk: Excess capacitance, ringing, slow rise time, arbitration/firmware conflicts, and multiple-master contention.
- Correction: Define one master. Estimate bus capacitance and select pull-ups from the required speed/rise time. Consider bus switches/buffers or divide the cluster into shorter branches. Add optional series damping footprints near the master and verify at the intended clock rate.
M7 — microSD interface lacks robust default-state control
- Affected:
CARD1,D3_CS,D8_MISO,D9_SCLK,D10_MOSI - Evidence: No dedicated SD CS/data pull-ups are present; card detect is isolated. Custom pin mapping differs from XIAO defaults.
- Risk: Unreliable startup, accidental card selection during boot, and failure with default SPI initialization.
- Correction: Add a 47–100 kΩ pull-up on CS and any other pull resistors required by the selected socket/card mode. Connect card detect to a GPIO if needed. Correct the D8/D9 routing or define custom pins explicitly in firmware and documentation.
M8 — GNSS supply and RF support are incomplete
- Affected:
U2,RF1,L1 - Evidence: GPS VBAT is tied to main 3.3 V; nearest clearly identified bulk capacitor is ~7.7 mm away and no close 100 nF bypass was proven. RF_IN is tied to RF1 and biased from VCC_RF through 47 nH without a documented full reference network.
- Risk: Cold starts after power loss, supply noise sensitivity, antenna mismatch, and uncertain passive/active antenna compatibility.
- Correction: Place 100 nF plus 4.7–10 µF directly at GPS VCC/GND. Add backup-cell/supercap support if hot/warm start retention is required. Implement the exact antenna bias/matching/ESD network from the ATGM336H datasheet and clearly specify passive versus active antenna use.
M9 — External connectors lack adequate ESD/protection evidence
- Affected: USB1, CARD1, RF1, CN1, CN2–CN4, OLED/header interfaces
- Evidence: BOM has no dedicated ESD arrays or connector TVS devices.
- Risk: Handling and cable transients can damage MCU, GPS, SD, charger, or fan circuitry.
- Correction: Add application-appropriate low-capacitance ESD protection at USB and RF; add TVS/series protection for externally cabled GPIO/I2C/UART as needed; protect battery and fan rails according to cable length and environment.
M10 — Power-via and +5 V neckdown rules are not current-driven
- Affected:
+5V,POWER_VDC,+3.3V,B+ - Evidence: +5 V contains widths down to 0.20 mm. POWER_VDC and +3.3 V each use only two named vias over long distribution routes. B+ has no named via in the source via table. Standard vias are 0.305 mm drill / 0.610 mm diameter.
- Risk: Local voltage drop and via heating where hundreds of milliamps or more change layers.
- Correction: Create current-based net classes. Keep high-current trunks wide; narrow only after a low-current branch point. Use multiple parallel power vias at charger, battery, regulator, fan, and rail transitions. Validate with actual copper weight and temperature-rise targets.
M11 — Connector polarity and module orientation require explicit production verification
- Affected: CN1, CN2–CN4, RF1, USB1, H1–H21
- Evidence: Battery pin 1 is positive and pin 2 is GND; fan pin 1 is GND and pin 2 is switched +5 V. Cable conventions vary. Machine data cannot prove intended mating orientation.
- Risk: Reversed battery/fan cables or incorrectly installed modules.
- Correction: Verify every footprint against the exact purchased connector and cable. Add large
+,−, pin-1, module-orientation, and switch-state silkscreen marks. Include an assembly drawing/photo in the release package.
Minor and manufacturing findings
N1 — TP4056 thermals need measured validation
The exposed pad has useful local ground-via density, but R17 likely sets a high charge current. Confirm actual programmed current, copper area, enclosure temperature, and thermal regulation. Reduce current if needed.
N2 — LDO/GPS high-frequency decoupling placement is inconsistent
Bulk 10 µF capacitors are generally within ~2.3–2.8 mm of TP6217 regulators, but 100 nF caps are often farther away. Place 100 nF at each active IC supply pin with a short ground loop.
N3 — Fan fault output is unused
U1 FLG is pulled up by R1 but is not routed to an MCU. Route it to a GPIO if fan fault reporting matters; otherwise document it as intentionally unused.N4 — Card-detect is unused
CARD1 CD is isolated. Connect it to a GPIO with a defined pull state if hot insertion/card presence must be detected.N5 — Drill package can be misinterpreted
Drill_PTH_Through.DRL already contains the 168 via drills, while Drill_PTH_Through_Via.DRL repeats the same via set. Confirm the fab’s expected submission and avoid double-processing duplicated drill coordinates.N6 — Annular ring is acceptable but should be fab-checked
The 0.305 mm drill in a 0.610 mm via leaves ~0.153 mm nominal annular ring. This is commonly manufacturable, but confirm finished-hole and registration rules with the selected fab.
N7 — XIAO modules are excluded from BOM/PnP
The ten modules appear as DNP placeholders and are not in the 129-placement assembly list. This is acceptable only if they will be manually fitted. Mark the assembly plan explicitly.
Confirmed positive observations
- The 2-layer Gerber set, top/bottom soldermask, top paste, BOM, and PnP are broadly coherent.
- All 129 PnP entries are top-side, so no bottom paste file is expected.
- Board outline is a simple ~88 mm × 88 mm rounded rectangle without detected cutouts.
- Main 3.3 V and ESP rail traces are 0.5 mm rather than minimum-width signal traces.
- TP4056 exposed-pad region includes multiple local GND vias.
- USB-C CC1 and CC2 each have the correct 5.1 kΩ sink pull-down topology.
Required revision plan
- Redesign the complete power tree: one protected USB-C input, power-path charger, single protected 1S battery connector,
SYSrail, and current-limited source behavior. - Power all XIAO modules only through VBUS/5 V: remove external injection into
3V3_OUT; size a 5 V converter/distribution network for the measured ten-module peak. - Correct/standardize pin mapping: use official XIAO UART/SPI defaults or explicitly document custom GPIO mapping. Rename nets by true signal direction and GPIO.
- Move to 4 layers and define net classes: uninterrupted GND plane, current-based power widths/vias, 50 Ω GNSS RF geometry, controlled USB pair if data is used.
- Add protection and local decoupling: USB/battery/fan/SD/RF ESD and fault protection; supply-pin bypass placement.
- Verify with finite release tests: ERC/DRC, source-to-Gerber netlist comparison, rail transient testing with all ten modules transmitting, charger/load-sharing tests, thermal imaging, RF/GNSS sensitivity testing, and connector polarity inspection.
Corrected Flux revision feasibility
The supplied
.epro2 contains editable EasyEDA Pro schematic and PCB records, but it is not a native Flux project. There is no reliable one-click editable PCB import path in this project session. A corrected Flux revision is feasible as a manual reconstruction, using the EasyEDA source for connectivity and the Gerbers/PnP/STEP for geometry verification. Because the existing architecture must change substantially for safety, reconstructing the corrected schematic first is preferable to attempting a geometry-perfect clone of the unsafe revision.Recommended execution sequence:
- Rebuild and review the corrected schematic in Flux.
- Freeze connector/module positions and board outline from the source package.
- Recreate a 4-layer placement with the corrected power/RF partitioning.
- Route, run ERC/DRC, and regenerate manufacturing outputs.
- Compare corrected BOM, PnP, outline, and interface locations against V2 before release.
Review limitations
The archive does not provide a selected fab stackup, copper weight, full native DRC rule report, enclosure/cable definitions, fan current, battery pack specification, firmware, or measured module current. Therefore exact impedance, temperature rise, battery runtime, I2C timing margin, and connector mating correctness must be verified during the redesign. These limitations do not change the confirmed stop-ship status of C1–C8.
Follow-up requirements and proposed pre-edit architecture — 2026-07-23
This section records the confirmed follow-up requirements and defines the recommended architecture before any schematic or PCB mutation. The original STOP-SHIP findings remain valid. No manufacturing package should be generated until the corrected schematic and layout have completed a new review.
Confirmed revision requirements
- One XIAO ESP32-C5 coordinator and nine wired XIAO ESP32-C5 scanner nodes.
- All ten modules may be powered and passively scanning simultaneously. Continuous simultaneous maximum-power transmission is not a normal operating requirement.
- I2C remains the primary wired transport. Preserve XIAO D4/SDA and D5/SCL and nominal 4.7 kΩ pull-ups unless bus analysis requires segmentation or different pull-up values.
- Removable 3.7 V single-cell rechargeable battery operation, with a user-selectable one-, two-, or three-cell runtime class.
- Normal operation while USB-C is connected and batteries are charging.
- Ordinary 5 V USB-C support where practical; USB-C PD in the 20–30 W class is approved.
- Fan is ANCHAOPU ACP2006, 5 V, 20 × 20 × 6 mm, two-wire, 0.10 A rated, connected at CN1/XH-2A.
- GPS remains ATGM336H-5N31, U2, LCSC C90770.
- Four-layer PCB is approved. Reliability, grounding, RF performance, EMI control, and power integrity take priority over minimum board cost.
- Preserve the 88 mm × 88 mm outline and external connector locations where they do not prevent a correct design.
Proposed battery architecture
Recommended architecture: one keyed battery-pack input with validated 1S pack variants
Do not retain three independent onboard battery connectors. The safe and practical method of preserving one-/two-/three-cell runtime options is one keyed pack connector that accepts a validated complete 1S battery pack assembly in one of these configurations:
- 1S1P, nominal 3000 mAh
- 1S2P, nominal 6000 mAh
- 1S3P, nominal 9000 mAh
The parallel cells must be matched and permanently assembled inside the pack by the pack manufacturer or qualified assembler. Each pack must include:
- Same chemistry and 4.2 V charge voltage across all approved variants
- Matched cells within each parallel pack
- Common pack protection/BMS for over-charge, over-discharge, over-current, and short circuit
- Pack NTC brought to the board
- Pack-identification resistor or memory value so firmware can limit charge and discharge behavior by approved pack type
- Keyed, touch-safe connector rated for the maximum current
The board-side pack interface should use at least
BAT+, BAT−, NTC, and PACK_ID. Add a board fuse and reverse-polarity/back-to-back-FET protection before the charger BAT node. The exact connector and protection FET/controller cannot be finalized until the approved pack current rating and mating connector are selected.Permitted and prohibited configurations
Permitted: one approved HellzGate 1S pack assembly connected at a time, in 1S1P/1S2P/1S3P capacity variants that share the same cell chemistry, charge voltage, connector, NTC behavior, and identification scheme.
Prohibited: separate loose cells or packs connected in parallel by the user; mixed capacity, chemistry, age, protection status, manufacturer, or state of charge; unprotected cells; series-connected packs; adapters that bypass
PACK_ID or NTC.Alternative if independent hot-swappable battery cartridges are mandatory
Each cartridge would need its own cell protection, NTC, identity, controlled charge path, discharge ideal diode, current measurement, and fault isolation. The main board would require one independent managed channel per cartridge. This is substantially more complex and is not recommended for the current 88 mm board unless true hot-swap expansion is a hard requirement.
Proposed power-path architecture
Provisional component direction
The following is the recommended functional chain; exact support-component values remain datasheet-driven work for the schematic phase:
- USB-C input: USB-C receptacle with VBUS TVS/ESD protection.
- Input eFuse: TPS25947-class 2.7–23 V eFuse with adjustable current limit, soft start, over-voltage protection, thermal protection, and true reverse-current blocking.
- PD controller: STUSB4500QTR standalone sink controller, configured for 12 V / 2.5 A preferred, 9 V / 3 A secondary, and 5 V fallback. It can also report default, 1.5 A, or 3 A Type-C current advertisement at 5 V.
- Charger/power path: BQ25895RTWT 1S switch-mode charger. It supports 3.9–14 V input, programmable input-current limit up to 3.25 A, charge current up to 5 A, NTC monitoring, NVDC power-path management, battery supplement operation, and an approximately 11 mΩ BATFET advertised for up to 9 A discharge.
- Main system rail: BQ25895
SYSfeeds a TPS61288RQQR-class synchronous boost converter producing regulatedSYS_5V. TPS61288 is a 15 A-switch device intended for single-cell Li-ion systems and is rated for up to approximately 35 W from a single-cell source when its thermal, inductor, and layout requirements are satisfied. - XIAO distribution: all ten XIAO modules receive power only at their VBUS/5 V pins. Their
3V3_OUTpins are not externally driven. Use current-limited load switches per node or small node group to support sequencing, fault isolation, and power measurement. - Peripheral 3.3 V: one documented synchronous buck regulator from
SYS_5Vsupplies GPS, microSD, OLED, I2C pull-ups, temperature sensors, and logic. The exact regulator and rating remain pending the display/SD current specification; provisional design allocation is at least 1 A with transient margin. - Battery connection: the single approved pack connects to BQ25895 BAT through the keyed connector, fuse, reverse-polarity/reverse-current protection, NTC, and pack-ID circuitry.
This topology creates separate
VBUS_RAW, VBUS_PROTECTED, SYS_BAT, SYS_5V, and PERIPH_3V3 domains. It removes the paralleled LDO outputs, eliminates external XIAO 3.3 V injection, provides true load sharing, and prevents USB/battery backfeed.Source-transition behavior
- With adequate USB power present, the charger powers
SYS_BAT, the boost converter maintainsSYS_5V, and remaining input power charges the battery. - If the load approaches the negotiated USB limit, BQ25895 input DPM reduces charge current first; battery supplement can support short load transients.
- When USB is removed, the BATFET maintains
SYS_BATfrom the battery and the 5 V boost continues without intentionally paralleling sources. - With no battery, an adequate USB source can operate the board through the charger SYS path.
- With a weak 5 V source, charging and scanner-node count are reduced before the source is overloaded.
Documented provisional power budget
Source data and assumptions
- ESP32-C5 official active-mode maxima used for supply sizing:
- 5 GHz Wi-Fi RX: 128 mA at 3.3 V per device
- 5 GHz Wi-Fi TX: 397 mA at 3.3 V per device
- XIAO onboard 5 V-to-3.3 V conversion efficiency is provisionally bounded at 85% for budgeting. This is a conservative engineering assumption, not a guaranteed Seeed specification.
- GPS datasheet values:
- Typical operation: less than 25 mA at 3.3 V
- Module peak: 100 mA, excluding antenna
- VCC_RF antenna short-circuit limit: 50 mA
- Fan rated current is 0.10 A. Because startup/stall current is unpublished, 0.30 A is reserved as a temporary 3× design allowance until measured.
- microSD, OLED, and final temperature-sensor currents are not specified in the supplied files. Their values below are explicit design allocations, not claimed component specifications.
5 V system rail budget
Table
| Load | Normal passive-scan allocation | Engineering peak allocation | Basis |
|---|---|---|---|
| 10 × XIAO ESP32-C5 | 0.99 A | 3.08 A | 128 mA RX / 397 mA TX at 3.3 V, converted from 5 V at 85% |
| Fan | 0.10 A | 0.30 A | Rated current / temporary startup reserve |
| GPS + antenna | 0.04 A | 0.11 A | Typical module plus antenna reserve / 100 mA + 50 mA at 3.3 V |
| microSD | 0.05 A | 0.20 A | Provisional allocation; exact socket/card peak must be verified |
| OLED/display | 0.05 A | 0.10 A | Provisional allocation; exact display must be identified |
| I2C muxes, temperature sensing, load-switch control | 0.03 A | 0.05 A | Provisional logic allocation |
| Subtotal | 1.26 A | 3.84 A | Before engineering margin |
| Margin | 25% | 20% | Continuous uncertainty / transient margin |
| Design result | 1.58 A at 5 V (7.9 W) | 4.61 A at 5 V (23.1 W) | Main sizing envelope |
Power-path sizing result
- Regulated
SYS_5Vtarget: 5 V, 5 A design class. - Preferred USB-C PD input: 30 W class.
- Preferred PDO: 12 V / 2.5 A; secondary PDO: 9 V / 3 A.
- At a conservative 85% total USB-to-5 V efficiency, the 23.1 W engineering peak requires approximately 27.2 W input. Therefore 9 V / 3 A is marginal at the absolute peak and 12 V / 2.5 A is preferred.
- Full engineering-peak operation and high-rate battery charging cannot be guaranteed simultaneously from a 30 W source. System operation takes priority; charge current must reduce dynamically.
Battery current and runtime implications
Using 88% provisional battery-to-5 V efficiency and the depleted-pack design voltage of 3.0 V:
- Normal scanning envelope:
7.9 W / 0.88 / 3.0 V ≈ 3.0 Abattery current. - Engineering peak:
23.1 W / 0.88 / 3.0 V ≈ 8.8 Abattery current.
An approved pack must therefore support at least approximately 4 A continuous for normal scanning with margin. Supporting the full engineering peak without load limiting requires a pack, connector, protection circuit, fuse, and PCB path rated for approximately 10 A. If the selected flat 3000 mAh pack cannot meet this safely, firmware/hardware must enforce a battery-mode power cap or a higher-discharge pack must be selected.
Approximate runtime at the 7.9 W normal envelope, assuming 80% usable nominal pack energy and 88% conversion efficiency:
Table
| Pack | Nominal energy | Approximate runtime |
|---|---|---|
| 1S1P 3000 mAh | 11.1 Wh | ~1.0 hour |
| 1S2P 6000 mAh | 22.2 Wh | ~2.0 hours |
| 1S3P 9000 mAh | 33.3 Wh | ~3.0 hours |
These are planning values; measured scanner current, cell discharge curves, temperature, and converter efficiency will change actual runtime.
Proposed USB-C/PD operating policy
Table
| Available source | Allowed behavior |
|---|---|
| 12 V / 2.5 A PD or equivalent 30 W PDO | Full ten-node scan operation; charging enabled and dynamically reduced as system load rises |
| 9 V / 3 A PD | Full scan operation; charging limited; little or no charging at engineering-peak load |
| 5 V / 3 A Type-C | Normal scanning expected; low-rate charging only if measured load leaves margin |
| 5 V / 1.5 A Type-C | Charging disabled; battery may supplement; firmware may reduce active nodes or scan duty cycle |
| Default-current 5 V source | Safe degraded mode only: coordinator plus a limited node set, no normal charging, fan still permitted for thermal safety |
The STUSB4500 reports the 5 V Type-C advertisement, while BQ25895 input-current DPM enforces the corresponding current limit. Power-up must start in a low-load state until source capability is known. Scanner load switches are then enabled in stages.
USB data and firmware update direction
- Do not attempt a ten-port USB hub or simultaneous hardware flashing in this revision.
- Use the central USB-C D+/D− pair for one reliable service interface, preferably coordinator diagnostics through a USB-UART bridge if the XIAO native USB pads cannot be accessed cleanly.
- Initial module programming may still use each XIAO module’s onboard USB connector before installation.
- Centralized scanner updates should use an application-level signed firmware transfer from the coordinator over I2C to each node’s OTA partition, one node at a time. This avoids pretending that the ESP32 ROM bootloader supports I2C flashing.
- Final selection depends on physical access to the coordinator USB connector, EN, and BOOT pads in the enclosure.
Proposed four-layer stackup and routing policy
Use a standard economical 1.6 mm four-layer FR-4 service from the selected fabricator. Exact dielectric thickness, copper weight, and controlled-impedance geometry must come from that fabricator before routing.
Table
| Layer | Purpose |
|---|---|
| L1 Top | Components; USB, GNSS RF, clocks, critical signals, and short power-stage loops |
| L2 Inner 1 | Uninterrupted solid GND plane; primary return reference for L1 |
| L3 Inner 2 | Power distribution for SYS_5V, SYS_BAT, PERIPH_3V3, and protected VBUS; avoid routing fast signals over plane boundaries |
| L4 Bottom | Low-speed signals and local GND copper; preserve continuous return paths and add stitching to L2 |
Required constraints:
- GNSS RF route: 50 Ω grounded coplanar waveguide or microstrip on L1 referenced to L2; exact width/gap calculated from the fab stackup; no vias; dense GND stitching at RF1 and beside the route.
- USB 2.0: 90 Ω differential on L1 referenced to L2; tightly coupled, no plane crossings, preferably no vias, and length mismatch less than 0.5 mm.
- XIAO antennas: no copper, traces, planes, components, or metal enclosure features in the official antenna keepout on any layer. Antennas should face outward where practical.
- Switching regulators: minimize hot loops; keep SW nodes small and away from GPS/RF, I2C, and antenna zones; use thermal-via arrays per regulator datasheets.
- Main 5 V rail: design for 5 A class with broad planes/pours, multiple power vias, and node branches protected by load switches.
- Battery path: design for up to 10 A only if full battery peak mode is approved; otherwise size to the enforced battery-mode current limit.
- GPS module: maintain continuous ground under the module and keep fan/switching return currents out of the GNSS ground/RF area.
GPS implementation resolved from the ATGM336H-5N31 documentation
- VCC operating range: 2.7–3.6 V; 3.3 V nominal.
- Place the documented 10 µF supply capacitor at VCC and add a close high-frequency ceramic bypass during schematic design.
- Active antenna reference: connect VCC_RF to the RF feed through 47 nH. The module provides antenna detection and limits antenna short-circuit current to 50 mA.
- Passive antenna reference: the datasheet shows an external AT2659 LNA with 6.8 nH, 0.1 µF, and 470 pF support components.
- The antenna interface must be close to RF_IN and impedance matched to 50 Ω.
- The module should be kept away from high-frequency, high-amplitude digital signals and should have ground fill below it.
The existing 47 nH network corresponds to the active-antenna reference direction. The exact antenna model and cable/connector remain required before finalizing ESD, bias current, and matching.
Fan-control direction
- Retain a protected 5 V fan branch but isolate it from GPS and peripheral 3.3 V with local bulk/high-frequency decoupling and, if measurement justifies it, a ferrite bead or LC input filter.
- Use a logic-controlled MOSFET or current-limited load switch with at least the provisional 0.30 A startup margin and fault reporting.
- Provide a hardware-default safe state. Preferred behavior is fan-on after MCU reset/failure unless a hardware temperature supervisor confirms a safe temperature.
- Use a dedicated board temperature sensor near the hottest module/power area plus battery NTC monitoring. A hardware over-temperature signal should be able to force the fan on independently of normal firmware.
- Exact temperature sensor, fan-on threshold, hysteresis, and shutdown threshold remain to be selected from enclosure thermal testing.
I2C transport direction
D4/SDA and D5/SCL are retained on every XIAO. A single 227–245 mm shared bus with ten MCU nodes remains a signal-integrity and firmware-arbitration risk. The provisional recommendation is to isolate scanner branches with I2C switches/buffers, while retaining the same D4/D5 pin assignment at every module. Use one coordinator as the only master, assign stable node identities, operate initially at 100 kHz, and provide pull-up/series-resistor footprints so measured rise time and ringing can be corrected.
Remaining decisions before schematic editing
- Battery expansion form: approve the recommended single keyed connector with 1S1P/1S2P/1S3P complete pack variants, or require independent hot-swappable cartridges despite the added protected-channel complexity.
- Exact battery pack(s): manufacturer part number, protection/BMS limits, maximum continuous/pulse discharge current, permitted charge current, NTC curve, dimensions, and connector.
- Battery-mode peak policy: must the board support the 23 W engineering peak from battery, or may firmware cap transmit duty/node count while on battery?
- USB-PD source policy: confirm that a 12 V / 2.5 A preferred PDO and 9 V / 3 A secondary PDO are acceptable requirements for full operation.
- Display: exact OLED/display part number and current requirement.
- microSD: required card class and worst-case write-current requirement.
- GPS antenna: exact active or passive antenna part, cable length, connector type, and required backup-retention behavior.
- I2C topology: approve branch isolation/multiplexing or require a single shared physical bus; define node addressing/enumeration behavior.
- Firmware service: confirm whether coordinator-only USB diagnostics plus I2C OTA updates is acceptable, and whether XIAO USB/BOOT/EN access is available in the enclosure.
- Thermal policy: maximum ambient, fan-on temperature, over-temperature shutdown point, and whether default fan-on behavior is acceptable.
- Mechanical freedom: maximum component height and whether power inductors/protection devices may force small connector shifts while preserving the board outline.
- Fabricator: selected PCB manufacturer/standard four-layer stackup so RF and USB geometries can be calculated rather than guessed.
Pre-edit disposition
The corrected schematic should not begin until decisions 1–4 are confirmed because they govern battery safety, converter sizing, charger configuration, and source behavior. Items 5–12 can be resolved during the schematic phase only if clearly marked as provisional and verified before layout. The current project remains STOP-SHIP, and no existing design artifacts or manufacturing files should be treated as release-ready.
Architecture approval decision table — clarification requested 2026-07-23
The battery and USB-PD architecture below is not approved yet. This section separates established requirements from proposed engineering choices and unresolved decisions. No schematic or PCB edits are authorized by this table.
Status legend
- Confirmed requirement: explicitly approved by the project owner.
- Proposed engineering choice: recommended technical implementation awaiting approval.
- Unresolved decision: missing selection, specification, measurement, or approval that prevents final design lock.
Master decision table
Table
| Topic | Status | Decision or requirement | Engineering basis / consequence |
|---|---|---|---|
| PCB layer count | Confirmed requirement | Four-layer PCB | Reliability, grounding, RF/GPS performance, EMI control, and power integrity take priority over minimum PCB price. |
| Release status | Confirmed requirement | STOP-SHIP remains active | No corrected schematic, PCB, or manufacturing package is approved. |
| Manufacturing outputs | Confirmed requirement | Generate no manufacturing files until the corrected schematic and PCB complete review | Prevents an unreviewed architecture from becoming an orderable release. |
| Battery topology | Proposed engineering choice | One standardized keyed 1S pack interface accepting approved 1S1P, 1S2P, or 1S3P complete pack assemblies | Prevents users from electrically paralleling independent packs while preserving 3000–9000 mAh runtime options. |
| Independent battery ports | Proposed engineering choice | Remove the three independent battery connectors | Independent hot-swap ports require three managed charge/discharge/protection channels and are not justified unless hot swap is mandatory. |
| Battery connector | Proposed engineering choice | Molex Micro-Fit 3.0 right-angle 6-circuit PCB header 43045-0600, mating receptacle 43025-0600 | Keyed and latched; 3.0 mm pitch; official part page lists up to 8.5 A per contact subject to wire, terminal, circuit count, and temperature derating. |
| Battery cable terminals | Proposed engineering choice | Molex female crimp terminal 43030-0038 for 18 AWG power conductors; suitable smaller-gauge terminals from the same qualified family for NTC/ID | 43030-0038 is specified for 18 AWG and listed at up to 8.5 A per contact under applicable conditions. |
| Battery pinout | Proposed engineering choice | Pin 1 BAT+, pin 2 BAT+, pin 3 PACK_NTC, pin 4 PACK_ID, pin 5 BAT−, pin 6 BAT− | Two parallel contacts per power polarity keep nominal contact current below 5 A at the 10 A pack-path peak. Final orientation must be checked against the Molex sales drawing before footprint release. |
| Capacity range | Proposed engineering choice | Approved complete packs from 3000 mAh through 9000 mAh: 1S1P/1S2P/1S3P | All packs remain electrically 1S and 4.2 V charge class; capacity changes charge time and permitted current, not connector voltage. |
| Pack identity | Proposed engineering choice | Resistor-coded PACK_ID; provisional codes 10 kΩ = 1S1P, 22 kΩ = 1S2P, 47 kΩ = 1S3P | Allows firmware to select charge-current and battery-mode limits. Exact tolerance, ADC divider, open/short detection, and unauthorized-pack behavior must be finalized in schematic review. |
| Pack temperature | Proposed engineering choice | 10 kΩ pack NTC brought to PACK_NTC | BQ25895 supports thermistor-qualified charging. Exact beta curve and JEITA resistor network must match the selected pack. |
| Pack protection | Confirmed requirement | Every approved pack must include its own 1S protection/BMS | Required functions: over-charge, over-discharge, discharge over-current, short-circuit protection, and a documented charge/discharge rating. Board protection is additional, not a substitute for the pack BMS. |
| Minimum pack discharge | Proposed engineering choice | 5 A continuous minimum and 10 A pulse minimum for every approved pack variant | Normal scanning is calculated near 3 A at a depleted battery; the engineering peak is approximately 8.8 A. Pulse duration must be defined by the selected pack/BMS and validated against the load profile. |
| Battery reverse-polarity protection | Proposed engineering choice | LTC4365-1-class controller with external back-to-back low-RDS(on) N-channel MOSFETs, configured for a valid single-cell voltage window | Operates from 2.5 V and provides reverse-supply, UV, and OV isolation. When enabled, the MOSFET channel permits normal charge and discharge current. Exact MOSFET pair and thresholds remain unresolved. |
| Battery fuse | Proposed engineering choice | Littelfuse 0451010.MRL, 10 A, 451 Series NANO2 very-fast-acting SMD fuse as the provisional board backup fuse | Provides a defined board-level fault element behind the protected pack. The time-current curve must be checked against converter inrush and the approved pulse duration before release. |
| Charger current | Proposed engineering choice | Pack-ID-dependent charging: provisional 1.5 A for 3000 mAh; up to 3 A for 6000/9000 mAh if pack, connector, thermals, and source permit | Keeps a 3000 mAh pack near a moderate 0.5 C rate while allowing larger packs to charge faster. BQ25895 input DPM reduces charging whenever system load consumes the source budget. |
| Exact pack MPN | Unresolved decision | No approved battery pack part number is selected | Required before finalizing NTC, protection thresholds, dimensions, charge current, pulse duration, connector cable, and enclosure fit. |
| Exact reverse-protection MOSFET | Unresolved decision | Select a dual/back-to-back N-MOSFET solution rated for at least 10 A at the available LTC4365 gate drive | Must have datasheet RDS(on) at the real gate voltage, suitable SOA, low thermal resistance, and sufficient copper area. |
Can one connector safely support 1S1P, 1S2P, and 1S3P?
Table
| Item | Status | Conclusion |
|---|---|---|
| Electrical voltage compatibility | Confirmed requirement | All approved packs must be 1S, nominal 3.7 V, 4.2 V charge class. |
| Connector compatibility | Proposed engineering choice | Yes. A single 6-pin Micro-Fit interface can support all three capacities because the voltage and pin functions are identical. Capacity is identified through PACK_ID. |
| Current compatibility | Proposed engineering choice | Yes, if every approved pack meets the same 5 A continuous / 10 A pulse minimum and the two parallel contacts per polarity are correctly wired and derated. |
| User error prevention | Proposed engineering choice | Use one keyed connector family and publish an approved-pack list. Reject unknown/open/short PACK_ID values by disabling charging and entering a conservative low-power mode. |
| Separate connector variants | Proposed engineering choice | Not recommended. Different connectors would encourage adapter use and increase wiring errors without adding electrical safety. |
| Final approval | Unresolved decision | Project owner must approve the standardized single-pack interface and capacity-ID policy. |
Exact meaning of battery-mode peak limiting
Battery-mode peak limiting does not mean turning off most scanners during normal use.
Table
| Function | Status | Battery-mode behavior |
|---|---|---|
| Ten modules powered | Proposed engineering choice | All ten remain powered during normal battery surveying. |
| Simultaneous passive Wi-Fi/BLE scanning | Proposed engineering choice | Allowed for all ten modules. The normal 7.9 W envelope already budgets ten receivers simultaneously. |
| Short radio reports | Proposed engineering choice | Allowed, but coordinator schedules reports so only a limited number of nodes transmit at high RF power at once. |
| Sustained simultaneous maximum-power TX from all ten modules | Proposed engineering choice | Limited on battery, especially with a 1S1P pack. This is the condition that drives the approximately 8.8 A depleted-pack peak. |
| Wi-Fi/BLE availability | Proposed engineering choice | Remains enabled on every node. Limits apply to TX power, transmit concurrency, and duty cycle—not to passive scanning capability. |
| SD writes | Proposed engineering choice | Large writes may be buffered/staggered so they do not coincide with maximum radio and fan transients. |
| Fan | Confirmed requirement | Thermal-safety fan operation is never suppressed to meet the power cap. |
| OLED/noncritical loads | Proposed engineering choice | May be dimmed or deferred during a current-limit event, but this is secondary to radio scheduling. |
| Weak USB fallback | Proposed engineering choice | A default-current 5 V source may require actual node load shedding; this is separate from normal battery peak limiting. |
| Final policy approval | Unresolved decision | Confirm that all-node scanning with staggered/capped TX is acceptable and that sustained ten-node maximum TX is not required on a 1S1P pack. |
Proposed pack-dependent current policy
- 1S1P: target normal battery current below approximately 4 A; allow short transients only within the approved 10 A pulse specification.
- 1S2P/1S3P: higher sustained TX concurrency may be permitted after pack ratings and thermal tests are known.
- Hardware protection remains the final boundary. Firmware scheduling is not a substitute for the pack BMS, fuse, charger current limits, or converter current limits.
Reconciled worst-case power budget including charging
System load
The prior rail calculation remains:
- Normal ten-node passive scanning envelope: 7.9 W at regulated 5 V.
- Engineering peak system envelope: 23.1 W at regulated 5 V.
- Regulated output target: 5 V / 5 A = 25 W.
At the provisional 85% end-to-end USB-to-5 V efficiency:
- Normal system input requirement:
7.9 W / 0.85 ≈ 9.3 W. - Engineering peak system input requirement:
23.1 W / 0.85 ≈ 27.2 W.
Charging demand
Table
| Charge setting | Battery charge power at 4.2 V | Approximate USB input allocation at 90% charger efficiency | Status |
|---|---|---|---|
| 1.5 A | 6.3 W | ~7.0 W | Proposed engineering choice for 3000 mAh pack |
| 3.0 A | 12.6 W | ~14.0 W | Proposed engineering choice for larger packs if approved |
Combined source demand
Table
| Operating condition | Approximate source demand | Result |
|---|---|---|
| Normal scan + 1.5 A charging | 9.3 W + 7.0 W = 16.3 W | Fits 9 V/3 A and 12 V/2.5 A PD with margin |
| Normal scan + 3.0 A charging | 9.3 W + 14.0 W = 23.3 W | Fits both PD profiles, with more margin at 12 V/2.5 A |
| Engineering peak + 1.5 A charging | 27.2 W + 7.0 W = 34.2 W | Exceeds 30 W; charging must be reduced or stopped |
| Engineering peak + 3.0 A charging | 27.2 W + 14.0 W = 41.2 W | Exceeds 30 W; charging must be stopped and peak may need slight limiting |
Confirmed engineering consequence: a 30 W input cannot support the full 23.1 W engineering system peak and high-rate charging simultaneously after conversion losses. BQ25895 input DPM and firmware power management must prioritize system operation and reduce charge current toward zero during peaks.
12 V / 2.5 A versus 9 V / 3 A USB-PD comparison
Table
| Criterion | 12 V / 2.5 A | 9 V / 3 A | Status / conclusion |
|---|---|---|---|
| Contract power | 30 W | 27 W | Confirmed calculation |
| Approximate usable power at 85% conversion | 25.5 W | 23.0 W | Confirmed calculation from the provisional efficiency assumption |
| Engineering peak system load | 23.1 W | 23.1 W | 12 V leaves ~2.4 W; 9 V is approximately 0.1 W short before charging |
| Normal scan margin after 7.9 W load | ~17.6 W | ~15.1 W | 12 V provides ~2.5 W additional charging/thermal margin |
| Cable/connector/eFuse current | 2.5 A | 3.0 A | 12 V reduces current; resistive loss is proportional to I², so the same resistance dissipates about 31% less at 2.5 A than at 3.0 A |
| Charger conversion ratio | Larger 12 V-to-~4 V step-down | Smaller 9 V-to-~4 V step-down | 9 V may reduce switching/conversion stress; exact efficiency must be measured or taken from the final BQ25895 operating-point curves |
| Voltage stress | Higher | Lower | 12 V requires more voltage margin; use 25 V-rated input capacitors and appropriately rated TVS/eFuse parts |
| Thermal location | Less cable/contact I²R heat; potentially more charger switching loss | More cable/contact I²R heat; potentially lower charger switching loss | Net board temperature cannot be declared without the final layout and load test |
| Full-load charging | Only low residual charge power at the engineering peak | No meaningful charging at the engineering peak; slight load limiting may be required | System operation must take priority on both |
| Normal-load charging | Supports proposed 1.5 A and 3 A settings if pack/thermals permit | Supports proposed settings but with less margin | 12 V preferred for larger packs and hot conditions |
| 5 V fallback | Same: STUSB4500 remains at 5 V when no PD contract exists and reports source current advertisement | Same | Neither profile removes the requirement for safe 5 V current enforcement |
| Preferred profile | Proposed engineering choice: first preference | Proposed engineering choice: second preference | Approval still required |
Standard 5 V fallback
- 5 V / 3 A provides 15 W input and approximately 12.8 W at the 5 V system rail under the 85% assumption. It supports normal scanning, with only modest charging margin.
- 5 V / 1.5 A provides 7.5 W input and approximately 6.4 W usable, below the 7.9 W normal envelope. Charging is disabled and the battery supplements or node duty is reduced.
- Default-current 5 V cannot support all ten nodes at the normal envelope. The board starts with scanner branches off, reads the advertised current, and enables only a safe load set.
Reconciliation of 5 V / 5 A and 30 W USB-PD
Table
| Item | Status | Meaning |
|---|---|---|
SYS_5V = 5 V / 5 A | Proposed engineering choice | This is the downstream regulated rail capability, equal to 25 W. It is not a claim that the USB connector directly supplies 5 A at 5 V. |
| USB-PD = 30 W | Proposed engineering choice | This is the upstream source contract, preferably 12 V / 2.5 A. Conversion loss reduces the available regulated 5 V output to approximately 25.5 W at the provisional 85% efficiency. |
| Compatibility | Confirmed calculation | A 30 W input is appropriately matched to a 25 W output rail, leaving only about 0.5 W at the assumed worst efficiency when the rail is actually at 5 A. |
| Charging at 5 A rail load | Confirmed engineering consequence | Charging must be zero or near zero. A larger USB-PD contract would be required to guarantee 5 V / 5 A output and simultaneous battery charging. |
| Normal scan operation | Confirmed calculation | At 7.9 W output, a 30 W source has substantial remaining power for battery charging. |
Items still requiring approval or exact source data
- Unresolved decision: approve or reject the Molex 43045-0600 / 43025-0600 standardized 6-pin battery interface and proposed pinout.
- Unresolved decision: approve one complete 1S pack at a time in 3000/6000/9000 mAh variants rather than independent battery ports.
- Unresolved decision: provide or select exact pack MPNs meeting 5 A continuous / 10 A pulse, pack BMS, NTC, dimensions, and charge-current requirements.
- Unresolved decision: approve all-ten-node passive scanning with staggered/capped simultaneous TX as the definition of battery peak limiting.
- Unresolved decision: approve 12 V / 2.5 A as the preferred full-power PDO and 9 V / 3 A as secondary.
- Unresolved engineering selection: choose and thermally validate the LTC4365 external MOSFET pair and verify the 10 A fuse time-current behavior.
- Unresolved measurement: measure the ACP2006 startup/stall current rather than relying on the provisional 0.30 A allocation.
- Unresolved measurement: measure one XIAO ESP32-C5 in the actual passive-scanning firmware to replace the 85% conversion assumption and chip-level receive-current envelope.
Approval gate
No schematic or PCB work begins until items 1–5 above are explicitly accepted or revised. The document remains an engineering proposal, not an approved design specification.
ESP32-C5 Node Cluster V2 — Production Readiness Review
Executive summary
Overall scores
Stop-ship findings
C1 — Three Li-ion battery connectors are directly paralleled
C2 — TP4056 is used without a true power path/load-sharing function
C3 — Battery temperature and pack protection are absent
C4 — U5 and U10 LDO outputs are directly paralleled
C5 — The XIAO ESP32-C5 `3V3` pins are output rails but are driven by external LDOs
C6 — Aggregate USB-C current is uncontrolled and potentially far above default-source capability
C7 — No USB VBUS fuse/eFuse or transient protection
C8 — XIAO UART/SPI net names and default pin functions do not match the official pinout
Major findings
M1 — XIAO power-mode control is implemented with discrete NPNs but remains unsafe
M2 — Existing module-pair LDOs do not have a demonstrated current or thermal margin
M3 — USB data pins are isolated and not orientation-paired
M4 — GNSS RF route is not demonstrably 50 Ω
M5 — 2-layer stackup is poorly suited to this density and RF/current mix
M6 — Shared I2C bus spans ten MCUs over long traces
M7 — microSD interface lacks robust default-state control
M8 — GNSS supply and RF support are incomplete
M9 — External connectors lack adequate ESD/protection evidence
M10 — Power-via and +5 V neckdown rules are not current-driven
M11 — Connector polarity and module orientation require explicit production verification
Minor and manufacturing findings
N1 — TP4056 thermals need measured validation
N2 — LDO/GPS high-frequency decoupling placement is inconsistent
N3 — Fan fault output is unused
N4 — Card-detect is unused
N5 — Drill package can be misinterpreted
N6 — Annular ring is acceptable but should be fab-checked
N7 — XIAO modules are excluded from BOM/PnP
Confirmed positive observations
Required revision plan
Corrected Flux revision feasibility
Review limitations
Follow-up requirements and proposed pre-edit architecture — 2026-07-23
Confirmed revision requirements
Proposed battery architecture
Recommended architecture: one keyed battery-pack input with validated 1S pack variants
Permitted and prohibited configurations
Alternative if independent hot-swappable battery cartridges are mandatory
Proposed power-path architecture
Provisional component direction
Source-transition behavior
Documented provisional power budget
Source data and assumptions
5 V system rail budget
Power-path sizing result
Battery current and runtime implications
Proposed USB-C/PD operating policy
USB data and firmware update direction
Proposed four-layer stackup and routing policy
GPS implementation resolved from the ATGM336H-5N31 documentation
Fan-control direction
I2C transport direction
Remaining decisions before schematic editing
Pre-edit disposition
Architecture approval decision table — clarification requested 2026-07-23
Status legend
Master decision table
Can one connector safely support 1S1P, 1S2P, and 1S3P?
Exact meaning of battery-mode peak limiting
Proposed pack-dependent current policy
Reconciled worst-case power budget including charging
System load
Charging demand
Combined source demand
12 V / 2.5 A versus 9 V / 3 A USB-PD comparison
Standard 5 V fallback
Reconciliation of 5 V / 5 A and 30 W USB-PD
Items still requiring approval or exact source data
Approval gate
