Job 3G1 Correction

Thought for 35 sec
Thought for 11 sec — Inspecting project components
Reading layout details of LTC4373HDD#TRPBF.
Looking at the board of LTC4373HDD#TRPBF.
Reading symbol pins.
Thought for a moment
Analyzing pin layout issues
I see that there are problems with the EP terminal, which was generated as a perimeter pin, and the thermal pad being unbound. The project is HellzGate, but I can't mutate external components. I wonder if I can fix it by checking the part layout or submitting a quality issue. The pin placement seems incorrect too: the left row should have pins ordered as OUT 1, GATE 2, SOURCE 3, IN 4, while the right row has issues with UV and EP placements as well. This definitely needs attention!
Addressing thermal pad issue
Oh no, the thermal pad is separate and
fatenerris

fatenerris

there are two pads "IN_5" and "GND_4" which look like they should simply be GND

flux

Those pads indicate the TPS259830ONRGER, not the LTC4373. They must not both be GND:
  • IN_5 / Thermal Pad 1 → IN
  • GND_4 / Thermal Pad 2 → GND
TI specifies two electrically distinct exposed pads; shorting both to GND would directly short the input rail. The footprint naming may be awkward, but that separation is electrically required.
Audit both footprints
Fix LTC4373 part
Inspect TPS259830 part
Remove bad LTC4373
Create repair plan

Refine this doc
Ask about this doc
Job 1F Hardware Failover Qualification - Revised
Scope and disposition
Analysis and documentation only. No schematic, PCB, routing, stack-up, BOM, or manufacturing file was modified.
Job 1F is not approved for implementation. The fail/restore logic architecture is now explicitly defined and the restore-delay component is selected. However, a manufacturer-guaranteed sub-10 us scanner power-isolation time has not been established. The prior statements that 5.97 us was supported/guaranteed and that 1.40 us was substantially qualified are withdrawn.
Evidence classification
  • Guaranteed: manufacturer min/max values under stated test conditions.
  • Calculated: arithmetic using guaranteed values and explicit assumptions.
  • Nominal estimate: uses typical-only dynamic data and requires characterization.
  • Unresolved: no suitable guaranteed value or exact system measurement exists.
System boundaries
  • U3 static USB output: 4.982 V minimum, 5.040 V nominal, 5.098 V maximum.
  • U8 battery ceiling: 3.0 V x 5 A x 88% / 5.1 V = 2.588 A calculated.
  • Engineering peak at SYS_5V: 4.61 A provisional calculated.
  • Distant-XIAO floor: 4.80 V design boundary.
  • Job 1E requires scanner isolation within 10 us if the 50 mV U3 ripple allowance remains.
  • The 1.838 A post-scanner load and 0.750 A headroom remain provisional calculations, not production-qualified measurements.
Revised architecture
Diagram



  
    
  
  
    
  











































"VBUS_PROTECTED"
"20k over node_10k divider"
"REF3425 2.5V"
"TLV3201 fast comparator"
"SN74LVC1G74 async CLR"
"PRE tied high"
"SN74LVC1G74"
"D tied high"
"STUSB ATTACH active"
"RESTORE_VALID logic"
"PDO2 or PDO3 POWER_OK"
"U2 PG"
"U3 PG"
"TPS3808G01 MR"
"Delayed RESET rising edge"
"SCANNER_ALLOW_LATCHED"
"Per-bank command"
"SN74LVC1G08"
"2N7002Q gate pull-down"
"Scanner-bank PFET gate"
"Gate-to-source pull-up"
Explicit fail-dominant latch circuit
The previous concept used both asynchronous preset and clear and merely stated that simultaneous assertion was prohibited. That is replaced.
  • Latch: TI SN74LVC1G74DCTR.
  • D is tied to PERIPH_3V3.
  • /PRE is tied permanently high through 10 kOhm and is never asserted.
  • /CLR is driven directly by USB_FAST_GOOD; comparator low means fault and asynchronously forces Q low.
  • Q is SCANNER_ALLOW_LATCHED; low is the safe state.
  • Clock is the rising edge of the delayed TPS3808 RESET output.
  • A fault concurrent with a restore clock cannot enable scanners because asynchronous /CLR=0 overrides CLK and D by the SN74LVC1G74 truth table.
  • /PRE and /CLR can never both be asserted because /PRE has no active drive path.
  • At no USB, battery-only startup, or 5 V fallback, the comparator keeps /CLR low; Q therefore initializes and remains low after the logic supply becomes valid.
This is the required fail-dominant implementation, not a timing convention.
STUSB4500 interface and stale POWER_OK protection
Documented STUSB4500 behavior:
  • POWER_OK2 and POWER_OK3 are active-low open-drain contract outputs.
  • At detachment, a previously asserted POWER_OK pin can remain asserted.
  • POWER_OK state is reinitialized only after a new attachment or STUSB reset.
  • Therefore POWER_OK2/3 cannot be used alone as attachment or restore permission.
Proposed interface:
  • Configure POWER_OK2 for accepted PDO2, 9 V / 3 A.
  • Configure POWER_OK3 for accepted PDO3, 12 V / 2.5 A.
  • Pull each to PERIPH_3V3 with 100 kOhm.
  • Decode PD_HIGH_POWER_OK when either active-low output is asserted.
  • Create ATTACH_OK by inverting the existing active-low STUSB ATTACH output.
  • Define:
    • RESTORE_VALID = ATTACH_OK AND PD_HIGH_POWER_OK AND USB_INPUT_PG AND U3_POWER_GOOD AND USB_FAST_GOOD.
  • Any detach deasserts ATTACH_OK and VBUS_EN_SNK; U2 PG and USB_FAST_GOOD also fall as the path collapses. A stale POWER_OK state therefore cannot keep RESTORE_VALID true or produce a restore clock.
  • NVM mapping and readback remain mandatory before relying on POWER_OK2/3.
High-power falling detector
Parts and threshold
  • TI TLV3201AIDBVR comparator.
  • TI REF3425IDBVR 2.5 V reference.
  • Yageo RT0603BRD0720KL 20.0 kOhm, 0.1% top resistor.
  • Yageo RT0603BRE0710KL 10.0 kOhm, 0.1% bottom resistor.
Using REF3425 2.49875-2.50125 V, TLV3201 offset +/-6 mV, and independent resistor corners:
  • Nominal threshold: 7.500 V.
  • Calculated conservative range: 7.468-7.532 V.
Overdrive and collapse-slope timing
The TLV3201 55 ns maximum propagation specification applies at the datasheet overdrive conditions, including 20 mV comparator-input overdrive. The divider ratio is approximately 1/3, so 20 mV comparator overdrive requires VBUS_PROTECTED to move approximately 60 mV past the actual trip point.
For a local collapse slope magnitude S in V/us:
  • Overdrive-development time is approximately 0.060 / S us.
  • Detector time is therefore 0.060 / S us + 0.055 us, before latch and scanner isolation.
Examples:

Table

VBUS collapse slopeTime to 20 mV input overdriveDetector bound after threshold crossing
1 V/us0.060 us0.115 us
0.1 V/us0.600 us0.655 us
0.01 V/us6.000 us6.055 us
No uploaded source defines a universal VBUS collapse slope. A slow collapse is less immediately hazardous because U3 retains input headroom while VBUS remains near 7.5 V, but the relationship between VBUS slope, U3 dropout, output ripple, and distant-XIAO voltage must be verified in simulation and bench tests. The 55 ns number must not be used alone as total fault-detection time.
No RC filter is approved on the fast comparator input until its added delay is included in the full slope calculation.
Restore-delay selection
Selected device: TI TPS3808G01DBVT, Flux-supported SOT-23-6 variant.
Connections:
  • VDD to PERIPH_3V3 with local 100 nF bypass.
  • SENSE held above its 0.405 V threshold from PERIPH_3V3.
  • MR driven by RESTORE_VALID; MR low immediately asserts RESET.
  • CT left open.
  • RESET open drain pulled to PERIPH_3V3 and connected to the SN74LVC1G74 CLK.
Guaranteed CT-open delay:
  • 12 ms minimum, 20 ms typical, 28 ms maximum over the stated TPS3808 conditions.
Behavior:
  • Any invalid restore condition drives MR low, discharges/restarts the delay, and keeps RESET low.
  • Only 12-28 ms of continuously valid ATTACH, high-power PDO, U2 PG, U3 PG, and fast-good state produces the RESET rising edge that clocks D=1.
  • Fast shutdown does not depend on TPS3808 assertion delay; comparator /CLR directly clears the latch.
The restore-delay selection is resolved.
Complete scanner-gate control topology
Proposed topology per bank
  • High-side PFET source to SYS_5V and drain to one scanner-bank VBUS rail.
  • Gate-to-source pull-up resistor provides default OFF.
  • Diodes Inc. 2N7002Q-7-F pulls the PFET gate low to turn the bank on.
  • TI SN74LVC1G08DCKRG4 generates BANK_ON = BANK_COMMAND AND SCANNER_ALLOW_LATCHED.
  • 1 kOhm series resistor from logic output to 2N7002 gate.
  • 100 kOhm 2N7002 gate-to-ground pull-down.
  • Logic and MOSFET command path is active only to turn the bank on. Fault behavior is removal of the pull-down; the PFET gate-to-source resistor turns the bank off.
Pull-down release and contention
  • SN74LVC1G08 maximum propagation at 3.3 V, -40 C to 125 C: 6 ns.
  • SN74LVC1G08 Ioff disables its output when unpowered; the 100 kOhm resistor then holds the 2N7002 off.
  • 2N7002 Ciss is 50 pF maximum at its specified test point. A 1 kOhm gate resistor gives 50 ns RC; five time constants are 250 ns before PCB parasitics.
  • During the transition, the PFET pull-up resistor and 2N7002 can contend. The pull-up value must limit this current to a safe continuous value for both devices and itself.
  • Example only: 220 Ohm at 5.211 V permits up to about 23.7 mA and dissipates about 124 mW while the bank is on; use at least a 250 mW resistor with temperature derating.
  • Once the 2N7002 becomes high impedance, the PFET gate rises through the pull-up.
  • Unpowered logic state is safe: LVC output is disabled by Ioff, 2N7002 gate is pulled low, and the PFET gate is pulled to source.
Dynamic timing limitation
The scanner PFET previously proposed was CSD25402Q3A. Its total gate charge is typical-only, not a production maximum. The examined alternative DMP2066LDM-7 also gives total gate charge and capacitance as typical-only and is not recommended for new designs. Integrated load switches examined, including TPS22918, TPS22930A, TPS22995, MIC9416x, and TPS259474 EN control, publish typical normal-disable timing rather than a suitable guaranteed sub-10 us maximum.
Therefore:
  • No guaranteed passive-fallback time is claimed.
  • The earlier 5.97 us supported/guaranteed statement is removed.
  • A 220 Ohm pull-up with CSD25402Q3A may provide a fast nominal transition, but its timing is only a nominal engineering estimate because Qg, Miller charge, voltage dependence, PCB capacitance, temperature, and parasitics lack a complete worst-case bound.
  • The 2N7002 release estimate is also conditional on its capacitance test point and added PCB capacitance.
  • The active scanner-gate control topology is defined, but the isolation-time requirement is not production-qualified.
Provisional post-shutdown load calculation
  • Ten-XIAO engineering allocation: 3.08 A.
  • Per-XIAO allocation: 0.308 A.
  • Nine scanner allocation: 2.772 A.
  • Provisional post-shutdown load: 4.61 A - 2.772 A = 1.838 A.
  • Provisional battery ceiling: 2.588 A.
  • Provisional calculated difference: 0.750 A.
These values remain provisional until fan startup/stall, OLED, microSD, XIAO firmware, converter efficiency, and other load maxima are measured or supported by guaranteed data. They are not production headroom claims.
Relevant live ERC inventory
Read-only ERC snapshot: 2026-07-24T17:47Z. No findings were dismissed, waived, or modified.
Directly relevant to Job 1F
  • U2 PGTH/FLT floating.
  • U2 OVLO/OVCSEL floating.
  • USB_INPUT_PG currently contains only U2 PG/AUXOFF and is not yet a completed pulled-up status signal.
  • U16-U24 VBUS pins: all nine scanner module VBUS inputs are floating and reported as missing power.
  • U13 scanner-command candidate pins P00-P04 are floating; many other U13 GPIO/address/interrupt pins are also floating.
  • U1 POWER_OK2 and POWER_OK3 have no active ERC findings because they are presently intentionally no-connect; Job 1F proposes using them only after NVM verification.
  • Existing U25 E2/H2 network has no ERC error but remains an engineering-invalid source-priority network; ERC does not validate its threshold behavior.
Other visible ERC findings not modified by Job 1F
  • Numerous floating scanner GPIO pins on U16-U24.
  • Additional floating/missing-power VBUS findings on D1 and U14.
  • Floating U11/U12 mux channels and reset/address pins.
  • Floating GPS, SD, fan, passive, and peripheral pins/components.
The project has hundreds of current ERC findings; Job 1F did not run a global remediation or alter any finding.
State behavior
Diagram



  
    
  
  
    
  












No

Yes

No

Yes








"Power rises"
"USB_FAST_GOOD low Async CLR forces allow low"
"All scanner commands blocked"
"High-power source fully valid?"
"TPS3808 requires 12-28ms valid"
"RESET rising edge clocks D high"
"Scanner banks may be staged on"
"USB_FAST_GOOD falls?"
Remaining approval blockers
  1. Select a production scanner isolation device or PFET whose normal-disable behavior can be bounded below 10 us using manufacturer-guaranteed dynamic limits.
  2. Alternatively, prove through approved characterization and production test that the selected PFET/gate network meets the required time with adequate statistical and environmental margin; this would be a process-controlled requirement, not a pure datasheet guarantee.
  3. Bound the VBUS collapse slope and U3 input-to-output transient relationship.
  4. Verify STUSB POWER_OK NVM mapping/readback and ATTACH behavior on hardware.
  5. Replace provisional load values with qualified maxima.
Conclusion
The fail-dominant latch, stale-POWER_OK protection, comparator threshold, and 12-28 ms restoration architecture are now explicit. The scanner-gate control topology and safe unpowered behavior are also defined. However, no supported or guaranteed passive/active scanner shutdown time is claimed, and Job 1F remains blocked from implementation approval.

  • Scope and disposition

  • Evidence classification

  • System boundaries

  • Revised architecture

  • Explicit fail-dominant latch circuit

  • STUSB4500 interface and stale POWER_OK protection

  • High-power falling detector

  • Parts and threshold

  • Overdrive and collapse-slope timing

  • Restore-delay selection

  • Complete scanner-gate control topology

  • Proposed topology per bank

  • Pull-down release and contention

  • Dynamic timing limitation

  • Provisional post-shutdown load calculation

  • Relevant live ERC inventory

  • Directly relevant to Job 1F

  • Other visible ERC findings not modified by Job 1F

  • State behavior

  • Remaining approval blockers

  • Conclusion

HellzGateC5 v2

HellzGateC5 v2 thumbnail
Production-readiness engineering review of the ESP32-C5 Node Cluster V2 EasyEDA design, including schematic, PCB, Gerbers, BOM, pick-and-place, power, RF, and battery safety.

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