• Eliminates uncontrolled pack-to-pack equalization current.
• One keyed interface supports all approved capacities.
• NTC and pack identification allow safe charge-current and power-limit selection.
• Two contacts per power polarity provide current and contact-resistance margin.
• Easier documentation and user support than three independent battery channels.

• Users swap a complete pack rather than adding arbitrary individual packs.
• Pack assemblies are more specialized than generic two-wire LiPo packs.
• A 1S3P pack may require a custom enclosure and qualified pack assembly.

• No exact battery pack MPN has been selected.
• A flat 3000 mAh pack may not meet the proposed 5 A continuous / 10 A pulse requirement.
• Connector derating, cable gauge, crimp quality, and pack BMS pulse duration require validation.
• PACK_ID cannot by itself prevent unsafe third-party adapters.

• Every approved pack is 1S, 4.2 V charge class, protected, and uses a compatible NTC.
• Minimum pack rating is 5 A continuous and 10 A pulse.
• Proposed charge limits are 1.5 A for 3000 mAh and up to 3 A for larger packs.

• Correct operation while charging.
• Prevents direct USB/battery/regulator paralleling.
• Supports 5–12 V input and dynamic input-current control.
• Battery can supplement short source-power deficits.
• NTC-qualified charging and firmware-readable status/faults.

• More complex than TP4056 and requires I2C configuration.
• Requires inductor, thermal copper, careful placement, and firmware initialization.
• High-rate charging is reduced or stopped during large system peaks.

• Charger and battery-boost thermal performance must be verified on the four-layer PCB.
• Incorrect startup firmware or register defaults could select an unsafe charge current.
• The exact NTC network and charge voltage cannot be finalized without the selected pack datasheet.

• BQ25895 input, system, and BATFET ratings remain suitable after detailed component-level calculations.
• Hardware defaults will enforce a conservative charge current before firmware configuration.

• 12 V / 2.5 A provides the full 30 W with lower cable and connector current.
• 9 V / 3 A is a widely available secondary profile.
• Standard 5 V sources remain usable in a controlled reduced-power mode.
• The PD controller can negotiate without relying on early MCU firmware.
• The eFuse adds soft start, current limiting, over-voltage, thermal, and reverse-current protection.

• 12 V causes greater voltage stress and may increase charger switching losses versus 9 V.
• 9 V has higher cable/contact I²R heating and only 27 W total.
• Full system peak and high-rate charging cannot occur simultaneously from a 30 W contract.
• Weak 5 V sources require reduced charging or scanner load shedding.

• Some power banks may offer 9 V but not 12 V.
• Incorrect PD NVM configuration could prevent the preferred contract.
• Charger/eFuse input capacitors and TVS must be rated for the selected PDO and hot-plug transients.

• The intended wall adapters or power banks provide 12 V / 2.5 A or 9 V / 3 A fixed PDOs.
• Approximately 85% worst-case USB-to-5 V efficiency is adequate for architecture sizing until measured.

• Removes the paralleled LDOs and unsafe XIAO 3.3 V backfeed.
• Predictable source transitions with one regulated system rail.
• Supports staged startup and degraded operation from weak USB sources.
• Centralized current and fault management.
• Separate peripheral 3.3 V rail isolates sensitive GPS and logic loads.

• Producing 25 W from a depleted 1S battery requires nearly 9 A.
• High-current boost conversion requires a large inductor, thermal copper, and careful EMI control.
• Per-node load switches increase BOM and routing area.

• The 88 mm board may require connector or component shifts to fit the power stage safely.
• A 1S1P battery may not support sustained maximum radio transmission.
• TPS61288 and its library footprint require full pin/thermal verification before use.

• Normal scan load remains near 7.9 W; engineering peak remains near 23.1 W.
• All ten modules can scan simultaneously, while sustained maximum-power transmissions can be scheduled or capped on battery.

• Prevents fan current pulses from contaminating GPS and 3.3 V rails.
• Hardware override provides fail-safe cooling.
• Fault reporting permits stalled/disconnected fan detection where electrically possible.
• Dedicated GPIO avoids the V2 D7/EN naming and UART conflict.

• Default fan-on behavior consumes power and creates noise during startup or MCU failure.
• A two-wire fan does not provide a tachometer signal.
• Filtering adds components and can reduce fan startup voltage if poorly selected.

• Actual startup and stall current remain unknown.
• Temperature thresholds and sensor placement have not been validated in the enclosure.
• Power PWM of a two-wire brushless fan may produce acoustic or electrical noise.

• 0.30 A is an adequate temporary startup allocation.
• On/off control is sufficient unless testing demonstrates a need for low-frequency PWM.

• Preserves the selected GPS module and active-antenna detection/short protection.
• Four-layer ground reference improves impedance control and noise rejection.
• Quiet supply and physical separation improve acquisition sensitivity.

• Controlled impedance depends on the selected fabricator stackup.
• Active and passive antenna implementations require different front ends.
• RF ESD adds capacitance and must be selected specifically for GNSS.

• The antenna model is not selected.
• Fan/power component placement may conflict with the existing RF connector location.
• Ten nearby ESP32 radios may reduce GNSS sensitivity without careful antenna placement and testing.

• The intended antenna is active because V2 already uses the documented 47 nH bias arrangement.
• RF1 remains an appropriate 50 Ω connector after footprint and cable verification.

• Multiple independent fault boundaries.
• Prevents a node or cable failure from disabling or damaging the complete system.
• Enables clear fault diagnosis and safer bring-up.
• Addresses the major reliability omissions in V2.

• Increased BOM, PCB area, and validation workload.
• Every protection device adds resistance, capacitance, or conversion loss.
• Incorrectly coordinated thresholds can cause nuisance trips or leave protection gaps.

• LTC4365 external MOSFET pair is not selected.
• The provisional 10 A fuse must be checked against actual pulse/inrush curves.
• RF/USB ESD components can degrade signal integrity if selected only by voltage rating.

• The selected battery pack includes functional internal protection.
• Protection thresholds will be coordinated with charger limits, converter UVLO, and firmware warnings.

1. Four-layer PCB with L2 as uninterrupted ground and L3 for power distribution.
2. One controlled 5 V system rail, nominally designed for 5 A.
3. Power every XIAO only through VBUS/5 V; never drive 3V3_OUT.
4. Remove the V2 TP4056 and paralleled-LDO architecture.
5. Use a switch-mode charger with real power-path management and NTC monitoring.
6. Use a protected 30 W USB-C PD input with ordinary 5 V fallback and enforced load limits.
7. Use one complete protected 1S pack at a time rather than user-paralleling independent packs.
8. Keep all ten modules available for simultaneous passive scanning; stagger or cap sustained maximum-power transmission on battery.
9. Use a protected and filtered fan branch with independent thermal override.
10. Implement the exact ATGM336H active/passive antenna reference and a controlled 50 Ω RF route.
11. Use layered battery, USB, ESD, thermal, and branch protection.

1. Approve the single standardized 1S pack architecture versus independently hot-swappable cartridges.
2. Approve Molex 43045-0600 / 43025-0600 and the proposed six-pin battery pinout, or request another keyed family.
3. Approve 5 A continuous / 10 A pulse as the minimum approved-pack rating.
4. Approve all-ten-node passive scanning with staggered/capped sustained TX as the battery peak-limit policy.
5. Approve 12 V / 2.5 A as preferred PD and 9 V / 3 A as secondary.
6. Decide whether default fan-on after firmware/reset failure is acceptable.
7. Select active or passive GPS antenna and provide the exact antenna/cable.

1. Exact battery pack MPN, BMS limits, NTC curve, dimensions, connector cable, and allowable charge current.
2. Actual XIAO current in the intended passive-scanning firmware.
3. ACP2006 startup/stall current.
4. Exact OLED and microSD peak currents.
5. Final charger, boost-converter, MOSFET, fuse, and thermal calculations.
6. Selected PCB fabricator stackup for USB and RF impedance geometry.
7. Enclosure ambient-temperature and component-height constraints.

• BQ25895 recommended ISYS is 5 A.
• SYS ranges approximately 3.5 V to 4.4 V, giving only 17.5 W to 22 W before boost losses.
• BATFET discharge is rated 6 A continuous and 9 A peak for up to 1 second.
• A depleted 1S battery supplying 25 W would require roughly 9.5 A before margin.

Diagram

• USB full-power operation bypasses the BQ25895 SYS and BATFET current bottlenecks.
• BQ25895 is retained as the managed 1S charger, but not as the main system-power conduit.
• USB and battery 5 V sources are reverse-blocked and ORed at SYS_5V; USB is set slightly higher for priority.
• The wide-input USB converter can support 5 V, 9 V, 12 V, or 15 V PD inputs while the BQ25895 always receives regulated 5 V, so 15 V is never applied directly to it.
• Battery discharge is deliberately current-limited before TPS61288. Full 25 W is guaranteed only from a qualified USB-PD source.

• Interface: Molex 43045-0600 PCB header and 43025-0600 mating housing.
• Power contacts: Molex 43030-0038 female terminals with 18 AWG wire; two contacts each for BAT+ and BAT-.
• Signals: PACK_NTC and PACK_ID, using qualified smaller-gauge Micro-Fit terminals.
• Pack types: complete protected 1S1P, 1S2P, or 1S3P assemblies, 3000-9000 mAh.
• Minimum provisional pack qualification: 5 A continuous and 10 A pulse, with the exact pulse duration supplied by the pack vendor.
• NTC: Semitec 103AT-2 curve or an explicitly compatible 10 kOhm NTC. BQ25895 0 C to 45 C reference network uses approximately 5.23 kOhm and 30.1 kOhm.
• ID proposal: 10 kOhm for 1S1P, 22 kOhm for 1S2P, 47 kOhm for 1S3P; unknown/open/short ID disables charging and invokes low-power mode.
• Pack protection: over-charge, over-discharge, charge/discharge over-current, and short-circuit protection are mandatory.

• SYS_5V: 5 V, 5 A design class.
• Full ten-node scan operation allowed.
• 23.1 W engineering system peak allowed from a qualified 30 W source.
• Charging is dynamically reduced toward zero as system load approaches the source limit.
• PD controller remains configurable for source-compatibility testing across 9 V / 3 A, 12 V / 2.5 A, and potentially 15 V / 2 A because the charger is isolated behind regulated 5 V.

• All ten modules remain available for passive Wi-Fi/BLE scanning.
• Battery discharge branch continuous target: approximately 5 A at the depleted-pack input, subject to exact eFuse/current-limiter tolerance.
• Approximate continuous output ceiling at 3.0 V and 88% efficiency: 13.2 W, comfortably above the 7.9 W normal scan envelope but below full simultaneous maximum TX.
• Sustained high-power transmissions and large SD writes are staggered or capped.
• Fan thermal safety is never disabled by the power ceiling.

• TPS61288 at 5 V / 5 A from 3.0 V would draw approximately 9.3 A average and about 10.2 A peak with a 2.2 uH inductor under conservative assumptions; this is below its 12 A minimum switch-current limit but too close to the BQ25895 BATFET limit for the original series architecture.
• In the refined battery branch, input current is limited near 5 A. A 2.2 uH inductor with at least 18 A saturation rating and low DCR provides substantial magnetic margin.
• TPS61288 requires 0.1 uF VIN bypass, at least 1 uF VCC decoupling, approximately 10 uF effective input capacitance plus bulk as needed, and typically three 22 uF effective output capacitors; final values follow the selected operating point and DC-bias analysis.
• BQ25895 uses a 1 uH charger inductor, at least 8.2 uF effective input capacitance with 25 V rating where applicable, 20 uF effective SYS capacitance, 10 uF BAT capacitance, and 4.7 uF REGN capacitance.
• BQ25895 /CE defaults high to disable charging until pack ID, NTC, and source capability are verified. Firmware programs charge current, disables or services the watchdog, then enables charging.

• Preserve the central USB-C D+ and D- pair.
• Route it to a USB-UART bridge for coordinator diagnostics and application-level firmware delivery on the official XIAO D6/TX and D7/RX pins.
• Initial programming and hard recovery remain available through each XIAO onboard USB connector or dedicated fixture pads.
• Use coordinator-managed application-level OTA transfer over I2C for scanner updates, one node at a time.
• Segment the nine scanner nodes behind I2C switches/buffers so each branch can be isolated and recovered; this also reduces bus capacitance and permits repeated slave addresses if required.
• A full UART/BOOT/EN multiplexing matrix for all nine scanners is not recommended because it adds substantial PCB complexity and does not eliminate the need for recovery access.