ESP32-C5 Review

Thought for 48 sec

flux

Independent read-back found a serious mismatch: J1/J3 PCB positions moved, but schematic J3 still reads as the old Yuandi TF-01A. I’m dispatching one focused correction; if the exact Molex replacement cannot persist, I’ll revert the partial placements and report the blocker.

Worked for 11 mins 9 sec

flux

The focused correction reports the Molex replacement has now persisted. I’m re-reading the live schematic and PCB one final time to resolve the earlier stale-state mismatch.

Thought for 1 min 8 sec

flux

The live source-of-truth still shows the old Yuandi connector, so the claimed replacement did not persist. I’m reverting the partial Job 3G1 edge-placement commits to #4a24e477 rather than leaving an unverified mixed state.

Worked for 1 min 7 sec

flux

Job 3G1 — BLOCKED and reverted

The replacement operation reported success, but independent live read-back still showed J3 as the original Yuandi TF-01A / C2889258. The Molex 5033981892 replacement therefore did not persist reliably.

To avoid leaving a mixed state with moved connectors and the old J3 footprint, all 13 partial Job 3G1/placement commits were reverted to checkpoint #4a24e477.

J3 remains the original Yuandi connector.
J1/J3 edge-placement changes were removed.
The premature change-log update was removed.
No XIAOs, routing, copper, outline, or unrelated circuitry remain changed.

Final status: BLOCKED. The exact Molex component replacement backend must persist successfully before service-edge placement can resume.

Diagnose replacement issue

Create Molex component

Try Hirose alternative

Keep Yuandi temporarily

Review commit diffs

Files

Schematic

Layout

3D View

SYS_5V Source Handoff Architecture Decision

Status — STOP / implementation not authorized by evidence

Decision timestamp: 2026-07-23 (current pass).
Verdict: Reject the present U4/U9 TPS259474 tied-output handoff. No source-selector or U2/U7 schematic mutation was made because the mandatory load-minimum and fully verified replacement gates are not satisfied. U1, U3, U8, U10, unrelated blocks, PCB layout, and manufacturing files remain unchanged.

Live-schematic evidence and load-minimum audit

Direct inspection of the persisted SYS_5V net finds only U4:OUT, U9:OUT, U10:VIN, U10 input capacitors C52/C53, and R33. The ten XIAO carrier VBUS pins are not on SYS_5V in the live netlist: coordinator X1 is on single-pin COORD_5V; U16–U24 VBUS pins are not members of SYS_5V. CN1 fan connector is also not a SYS_5V member. Therefore the requested “every present SYS_5V load” proof cannot honestly include the ten modules or fan as electrically present loads.

Table

Intended/direct consumer	Manufacturer evidence	Minimum verified input	Result
10 × Seeed XIAO ESP32-C5 VBUS	Seeed official wiki/schematic identifies VBUS/5V feeding SGM6029CYG/TR. SGMicro specifies SGM6029 VIN 1.95–5.5 V, but no manufacturer-guaranteed minimum VBUS for regulated 3.3 V at the XIAO’s actual load was found. Buck dropout/max-duty behavior is load dependent.	Not established	Blocking evidence gap; do not assume 4.75 V.
U10 LMR33630	TI recommended VIN starts at 3.8 V; completed external UVLO nominal on/off 4.296/3.947 V, resistor-only ON corners 4.2355–4.3581 V plus IC threshold tolerance.	External turn-on worst corner not fully restated with IC tolerance; nominal 4.296 V	Not limiting versus intended 5 V modules, but not the only intended load.
Fan branch	Project specification calls for 5 V ACP2006 fan, but live CN1 is not connected to `SYS_5V`; exact fan MPN/datasheet and startup/stall minimum voltage remain pending.	Not established	Blocking evidence gap.
Other direct persisted SYS_5V consumers	None beyond U10 and passives in the live netlist.	—	The intended architecture is incompletely wired.

Highest documented minimum requirement: cannot be established from manufacturer data presently attached/available. The XIAO and exact fan minimum-voltage requirements are unresolved, and their VBUS/power pins are not connected to SYS_5V in the persisted netlist.

BAT_5V worst-case calculation

U8 TPS61288 uses R10 = 73.2 kΩ ±1% and R11 = 10.0 kΩ ±1%. TI guarantees feedback reference 0.588–0.612 V over the stated electrical-characteristic conditions.

Nominal setpoint:

V_{BAT5,nom}=0.600\left(1+\frac{73.2}{10.0}\right)=4.992\text{ V}

Static low corner from reference and independent resistor tolerances:

V_{BAT5,static,min}=0.588\left(1+\frac{73.2\cdot0.99}{10.0\cdot1.01}\right)=4.8069\text{ V}

This is before load-transient droop, ripple, PCB/interconnect loss, thermal/current-limit behavior, capacitor tolerance/temperature/aging/DC-bias, and unverified compensation margin. U8 has 12 A minimum guaranteed switch peak current (under the datasheet condition), 160 °C typical thermal shutdown, and external compensation. The project power budget gives 23.1 W engineering USB peak (4.62 A at 5 V), but battery operation is intentionally limited to about 13.2 W output from a 5 A depleted-pack input assumption. The handoff stage itself must preserve the full 5 A USB design class; battery-mode instantaneous policy/load data are not yet a verified waveform.

Accordingly, a defensible loaded/ripple/thermal BAT_5V_min is lower than 4.8069 V but cannot be numerically closed with current evidence.

TPS259474 U4/U9 hold-up verdict

Per TI TPS25947 Rev. C, full forward recovery after reverse blocking requires VFWDTH = 83–125 mV; required maximum 125 mV is used. tSWRCB = 50 µs applies after the threshold condition is met.

Using even the optimistic static U8 low corner:

V_{SYS,crossover,max}=4.8069-0.125=4.6819\text{ V}

Actual floor is lower after load regulation, ripple, capacitor ESR and converter/source impedance. This cannot be compared as passing against every load because XIAO/fan manufacturer minima are absent. It is also below the conventional USB 4.75 V floor, which is explicitly not adopted as a load requirement here.

For a load current I, capacitance needed only for an additional droop \Delta V during recovery is:

C_{eff}\ge\frac{I\,t}{\Delta V}

At 5 A and 50 µs this is 250 µC/ΔV; for only 50 mV additional droop it requires 5,000 µF effective, before threshold-crossing time, ESR step (I·ESR), tolerance, temperature, aging, and DC bias. Practical margin would require substantially more and controlled ESR/inrush. Existing SYS_5V has U10’s 22 µF input ceramic plus 220 nF bypass only; no verified hold-up bank exists. Large bulk would also require U3/U8 stability, startup, source-stage inrush and eFuse energy validation.

Formal verdict: existing U4/U9 ORing is rejected. It cannot meet a production no-brownout claim at the static U8 low corner, and practical hold-up/inrush/stability margin is not proven.

Replacement architecture search and candidate dispositions

Flux library was searched first, followed by current manufacturer datasheets.

Table

Candidate	Disposition
TPS2117DRLR	Reject: integrated mux is 4 A, below the required 5 A continuous design class.
LTC4417CUF/CGN family	Active and present in Flux; prioritized 3-input controller with external back-to-back P-channel MOSFETs and VALID outputs. Reject for this pass: ADI specifies reverse-connect threshold 30–200 mV and 8 µs invalid detection, plus 0.7–3.2 µs break-before-make. At the maximum 200 mV threshold, the optimistic U8 static low corner implies about 4.607 V before additional droop. It therefore does not close the unknown load-minimum requirement. A source must also be valid 100–412 ms before use.
LTC4416 family	Active Flux entries exist, but a complete, manufacturer-verified 5 A priority/reference implementation, status behavior, switchover floor and exact external-FET network were not closed in this pass. Not selected.
LM74700-Q1 / LM74610-Q1	Useful external-FET ideal-diode controllers and available in Flux, but not complete deterministic dual-input priority muxes; extra hardware priority/validity logic would need full verification. Not selected.
SQ4435EY-T1_GE3 P-FET	Flux-available active candidate, 30 V, 15 A, RDS(on) max 31 mΩ at VGS = −4.5 V. Two back-to-back FETs per input would dissipate about `5²×0.062 = 1.55 W` per conducting channel at the guaranteed resistance before hot derating—thermally unattractive and not a completed solution.

No candidate was both fully verified against the unresolved load floor and completed with an exact production controller/FET/passive network. Per the explicit stop rule, no controller or undersized substitute was invented or placed.

Source-state table (current/rejected architecture)

Table

State	Conducting/blocked path	Minimum estimate	Policy/status dependency
No source	U4/U9 intended off; reverse paths blocked by back-to-back FETs	0 V	EN/UVLO support incomplete; status not valid.
Battery only	U8→U9→SYS intended	Below 4.8069 V loaded; exact floor open	Battery load ceiling and BAT_SOURCE_PG incomplete.
USB only	U3→U4→SYS intended, but U4 IN is presently `Net 1`, not USB_5V	Not validly connected	U4 misconnection is an implementation blocker.
USB insertion during battery	Higher USB intended to reverse-block U9	Unproven	Converter-loop and threshold interaction untested.
Both valid	USB nominally preferred by voltage offset	Unproven	No deterministic hardware priority.
USB removal	U9 recovery after up to 125 mV differential + 50 µs	≤4.6819 V before dynamic losses at optimistic static U8 corner	Fails production proof.
Weak/collapsing USB + battery	Potential threshold hunting/eFuse latch/load shedding interaction	Unproven	Requires hardware priority/valid-window design and coordinator load policy.
Battery fault + USB	USB path should carry if valid	U4 wiring/support incomplete	Fault/status nets incomplete.
Source OV/UV	Corresponding TPS path intended off	May interrupt SYS	Threshold networks incomplete.
Selector fault	Latch-off possible; no guaranteed alternate-path behavior	Undefined	Requires bench fault injection and named valid/fault outputs.

U2/U7 completion status

U2 and U7 were not modified. Their UVLO/OVLO/PGTH/PG pull-up, dV/dt, ITIMER and exact production-passive completion depends on verified downstream capacitance, source-selector architecture, inrush allocation, exact pack/fan/module data, and selected status rail. Applying values now would violate the requirement not to guess and could invalidate source-loop/inrush coordination. Existing generic R1/C1/C5 and R3/C3/C7 remain intentionally unchanged.

Focused validation

No schematic mutation occurred; therefore no caused ERC/SLC finding exists. Per instruction, no global ERC was run. Focused ERC/SLC was not run because the mandatory stop gate occurred before any changed designators existed; known incomplete U2/U7/U4/U9 support remains unclaimed.

Exact blockers and next actions

Obtain manufacturer-guaranteed minimum VBUS for the complete XIAO ESP32-C5 at required peak load, or qualify a project minimum by bench characterization with explicit margin.
Select the exact ACP2006 fan MPN/datasheet and establish run/start/stall minimum voltage/current.
Correct the incomplete intended load connectivity plan: identify/load-switch every XIAO/fan branch that is meant to be fed by SYS_5V (without touching unrelated blocks until authorized).
Produce U8 worst-case loaded transient/ripple result using exact capacitor DC-bias curves, compensation, inductor tolerance/DCR, battery input corner, thermal model and verified battery-mode instantaneous waveform.
Re-evaluate a priority controller whose guaranteed connection threshold plus delay leaves margin above the established load minimum; fully source exact controller, back-to-back FETs and passives in Flux before mutation.
Only after source selection, complete coordinated U2/U7 thresholds, inrush, ITIMER and status networks.

Remaining bench/layout tests

USB insertion/removal and weak-source collapse across temperature; U8 minimum-input/load transient and loop response; selector reverse leakage and cross-conduction; eFuse UV/OV/current-limit/latch reset; inrush with final effective capacitance; external-FET SOA/thermal; 5 A copper/via temperature rise; XIAO brownout behavior; fan startup/stall behavior; status timing and fault injection.

Capacity

Remaining ACU count is not exposed by available project tools.

Status — STOP / implementation not authorized by evidence
Live-schematic evidence and load-minimum audit
BAT_5V worst-case calculation
TPS259474 U4/U9 hold-up verdict
Replacement architecture search and candidate dispositions
Source-state table (current/rejected architecture)
U2/U7 completion status
Focused validation
Exact blockers and next actions
Remaining bench/layout tests
Capacity