Rev A Locked Architecture Details
Run AD5940 datasheet limits review only.
Do not modify schematic wiring.
Do not add components.
Do not change nets.
Review the AD5940 placeholder against datasheet/application-circuit requirements and identify what must be locked before PCB layout.
Check:
- Rail requirements:
- AVDD valid voltage range
- DVDD valid voltage range
- IOVDD / digital I/O rail requirement
- REG_1V8 role
- whether DVDD_AD5940 may remain tied to MCU_3V3: yes/no/uncertain
- whether separate 1.8 V rail placeholder is required: yes/no/uncertain
- SPI/logic compatibility:
- whether STM32L552 3.3 V SPI can directly connect to AD5940: yes/no/uncertain
- whether level shifting may be required: yes/no/uncertain
- BioZ/EIS pins:
- map placeholder nets to likely AD5940 pins/functions: AD5940_I_PLUS_PATH AD5940_I_MINUS_PATH AD5940_V_PLUS_PATH AD5940_V_MINUS_PATH AD5940_CURRENT_SENSE_P AD5940_CURRENT_SENSE_N AD5940_EXC_MON AD5940_AIN_MON
- Application-circuit blockers:
- required external references
- required RTIA/RLOAD/RCAL components
- required clock/crystal if any
- required decoupling not already represented
- required reset/interrupt/control pins
- Pre-layout decision: Choose one: A. Keep AD5940 as placeholder only B. Add separate 1.8 V LDO placeholder C. Add level-shifter placeholder only D. Split DVDD_AD5940 from MCU_3V3 E. Need human datasheet review before schematic changes
Report only:
- AD5940 rail blockers
- SPI/logic blockers
- missing application-circuit components
- recommended next schematic action
- whether current AD5940 section is safe for PCB layout: yes/no
Thought for 7 sec
I’ll run a read-only AD5940 datasheet-limits review against the current placeholder section, check rails, SPI logic, pin-role mapping, and application-circuit gaps, then report only the blockers and next action.
Worked for 1 min 10 sec
STOP
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Option B Verification Report
Scope
Read-only verification of Option B electrode architecture, mux mapping, and calibration bank state.
1. Electrode inputs
- E1 exists: PASS
- E2 exists: PASS
- E3 exists: PASS
- E4 exists: PASS
- E5 exists: PASS
- E6 exists: PASS
- E7 exists: PASS
- E8 exists: PASS
- E1-E8 are the live electrode nets used on mux IN0-IN7: PASS
2. CAL_COM
- CAL_COM exists: PASS
- CAL_COM is internal-only calibration/common reference net: PASS
- CAL_COM is not labeled E8: PASS
- CAL_COM is not connected to mux IN7: PASS
3. Mux channel map on all four muxes
Verified on MUX_I_PLUS, MUX_I_MINUS, MUX_V_PLUS, and MUX_V_MINUS.
- IN0 = E1: PASS
- IN1 = E2: PASS
- IN2 = E3: PASS
- IN3 = E4: PASS
- IN4 = E5: PASS
- IN5 = E6: PASS
- IN6 = E7: PASS
- IN7 = E8: PASS
- IN8 = CAL_OPEN: PASS
- IN9 = CAL_SHORT: PASS
- IN10 = CAL_100R: PASS
- IN11 = CAL_1K: PASS
- IN12 = CAL_10K: PASS
- IN13 = CAL_1K_PAR_10NF: PASS
- IN14 = CAL_10K_PAR_1NF: PASS
- IN15 = CAL_SERIES: PASS
4. Calibration bank
- R_CAL_SHORT = 0 ohm between CAL_SHORT and CAL_COM: PASS
- R_CAL_100R = 100 ohm between CAL_100R and CAL_COM: PASS
- R_CAL_1K = 1 kohm between CAL_1K and CAL_COM: PASS
- R_CAL_10K = 10 kohm between CAL_10K and CAL_COM: PASS
- R_CAL_1K_PAR_10NF = 1 kohm between CAL_1K_PAR_10NF and CAL_COM: PASS
- C_CAL_1K_PAR_10NF = 10 nF, dielectric C0G/NP0, between CAL_1K_PAR_10NF and CAL_COM: PASS
- R_CAL_10K_PAR_1NF = 10 kohm between CAL_10K_PAR_1NF and CAL_COM: PASS
- C_CAL_10K_PAR_1NF = 1 nF, dielectric C0G/NP0, between CAL_10K_PAR_1NF and CAL_COM: PASS
- R_CAL_SERIES_100R = 100 ohm between CAL_SERIES and CAL_SERIES_MID: PASS
- R_CAL_SERIES_1K = 1 kohm between CAL_SERIES_MID and CAL_COM: PASS
- C_CAL_SERIES_10NF = 10 nF, dielectric C0G/NP0, between CAL_SERIES_MID and CAL_COM: PASS
5. Additional confirmations
- No X7R, X5R, Y5V, Z5U, electrolytic, or tantalum capacitors in the calibration paths checked: PASS
- CAL_DUMMY_RC is not part of the primary mux map: PASS
- AD5940 added: NO
- MCU added: NO
- Connector components added: NO
6. Missing nets
None of the requested Option B nets were missing in the final logical netlist.
7. Duplicate labels
- Multiple Net Portal instances exist for some shared nets such as CAL_COM and several mux-control/map labels.
- This is expected portal duplication, not duplicate logical net names in the verified Option B primary map.
- No duplicate logical names were found among E1-E8, CAL_SHORT, CAL_OPEN, CAL_100R, CAL_1K, CAL_10K, CAL_1K_PAR_10NF, CAL_10K_PAR_1NF, CAL_SERIES, or CAL_COM.
8. Accidental shorts
- No unintended logical short was found in the final verified primary mux map.
- The only intentional zero-ohm short element is R_CAL_SHORT between CAL_SHORT and CAL_COM.
9. Wrong mux mappings
None found in the final readback. The Option B primary map is logically consistent.
10. Wrong component values
None found in the requested Option B calibration bank items.
11. Unresolved ERC / review issues
The project still has unresolved review issues unrelated to the requested read-only verification pass:
Electrical Rule Checks
- Floating Pin warnings: 3
- Floating pin: CAL_SERIES_MID:P1
- Floating pin: MUX_I_PLUS S14 - MUX_I_MINUS S14:P1
- Floating pin: MUX_I_PLUS S14 - MUX_I_MINUS S14:P1
Design Rule Checks
- Airwires errors: 97
- The current review is dominated by unrouted PCB airwires and related layout connectivity issues.
Overall assessment
Option B logical architecture and the requested calibration / mux state verify correctly.
The main remaining issues are review findings in layout/ERC, not a failure of the requested Option B mux/channel or calibration definitions.
Scope
1. Electrode inputs
2. CAL_COM
3. Mux channel map on all four muxes
4. Calibration bank
5. Additional confirmations
6. Missing nets
7. Duplicate labels
8. Accidental shorts
9. Wrong mux mappings
10. Wrong component values
11. Unresolved ERC / review issues
Electrical Rule Checks
Design Rule Checks
Overall assessment
