Rev A Locked Architecture Details

Run AD5940 datasheet limits review only.
Do not modify schematic wiring. Do not add components. Do not change nets.
Review the AD5940 placeholder against datasheet/application-circuit requirements and identify what must be locked before PCB layout.
Check:
  1. Rail requirements:
  • AVDD valid voltage range
  • DVDD valid voltage range
  • IOVDD / digital I/O rail requirement
  • REG_1V8 role
  • whether DVDD_AD5940 may remain tied to MCU_3V3: yes/no/uncertain
  • whether separate 1.8 V rail placeholder is required: yes/no/uncertain
  1. SPI/logic compatibility:
  • whether STM32L552 3.3 V SPI can directly connect to AD5940: yes/no/uncertain
  • whether level shifting may be required: yes/no/uncertain
  1. BioZ/EIS pins:
  • map placeholder nets to likely AD5940 pins/functions: AD5940_I_PLUS_PATH AD5940_I_MINUS_PATH AD5940_V_PLUS_PATH AD5940_V_MINUS_PATH AD5940_CURRENT_SENSE_P AD5940_CURRENT_SENSE_N AD5940_EXC_MON AD5940_AIN_MON
  1. Application-circuit blockers:
  • required external references
  • required RTIA/RLOAD/RCAL components
  • required clock/crystal if any
  • required decoupling not already represented
  • required reset/interrupt/control pins
  1. Pre-layout decision: Choose one: A. Keep AD5940 as placeholder only B. Add separate 1.8 V LDO placeholder C. Add level-shifter placeholder only D. Split DVDD_AD5940 from MCU_3V3 E. Need human datasheet review before schematic changes
Report only:
  • AD5940 rail blockers
  • SPI/logic blockers
  • missing application-circuit components
  • recommended next schematic action
  • whether current AD5940 section is safe for PCB layout: yes/no
I’ll run a read-only AD5940 datasheet-limits review against the current placeholder section, check rails, SPI logic, pin-role mapping, and application-circuit gaps, then report only the blockers and next action.
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Calibration Bank Verification Report
Date: 2026-05-22 Project: Bench EchoSpec AFE V7 Scope: Read-only verification pass of the calibration bank
Overall Status
  • Calibration bank structures requested by the user are present.
  • CAL_COM exists and no E8 net label or E8 component label was found.
  • The requested resistor and capacitor values are present.
  • All calibration capacitors currently carry C0G/NP0 metadata.
  • No muxes, electrodes, or AD5940 components were found in the schematic.
  • There are review issues still present, primarily PCB airwires and floating net-portal pins.
1. CAL_COM / E8 Check
  • CAL_COM net exists: PASS
  • E8 net label exists: FAIL NOT FOUND (desired result)
  • E8 component/designator exists: FAIL NOT FOUND (desired result)
  • Conclusion: CAL_COM exists and is not labeled E8.
2. Required Calibration Nets
All requested nets were found:
  • CAL_100R: PASS
  • CAL_1K: PASS
  • CAL_10K: PASS
  • CAL_1K_PAR_10NF: PASS
  • CAL_10K_PAR_1NF: PASS
  • CAL_SERIES: PASS
  • CAL_SERIES_MID: PASS
  • CAL_DUMMY_RC: PASS
  • CAL_DUMMY_MID: PASS
3. Component Value and Connectivity Checks
Simple resistor standards
  • R_CAL_100R = 100 ohms between CAL_100R and CAL_COM: PASS
  • R_CAL_1K = 1000 ohms between CAL_1K and CAL_COM: PASS
  • R_CAL_10K = 10000 ohms between CAL_10K and CAL_COM: PASS
Parallel RC standards
  • R_CAL_1K_PAR_10NF = 1000 ohms between CAL_1K_PAR_10NF and CAL_COM: PASS
  • C_CAL_1K_PAR_10NF = 10 nF, dielectric C0G/NP0, between CAL_1K_PAR_10NF and CAL_COM: PASS
  • R_CAL_10K_PAR_1NF = 10000 ohms between CAL_10K_PAR_1NF and CAL_COM: PASS
  • C_CAL_10K_PAR_1NF = 1 nF, dielectric C0G/NP0, between CAL_10K_PAR_1NF and CAL_COM: PASS
Series + parallel branch standard
  • R_CAL_SERIES_100R = 100 ohms between CAL_SERIES and CAL_SERIES_MID: PASS
  • R_CAL_SERIES_1K = 1000 ohms between CAL_SERIES_MID and CAL_COM: PASS
  • C_CAL_SERIES_10NF = 10 nF, dielectric C0G/NP0, between CAL_SERIES_MID and CAL_COM: PASS
  • Parallel condition for R_CAL_SERIES_1K and C_CAL_SERIES_10NF between CAL_SERIES_MID and CAL_COM: PASS
Dummy RC placeholder network
  • R_CAL_DUMMY_SERIES = 1000 ohms between CAL_DUMMY_RC and CAL_DUMMY_MID: PASS
  • R_CAL_DUMMY_PAR = 10000 ohms between CAL_DUMMY_MID and CAL_COM: PASS
  • C_CAL_DUMMY_PAR = 100 nF, dielectric C0G/NP0, between CAL_DUMMY_MID and CAL_COM: PASS
  • Parallel condition for R_CAL_DUMMY_PAR and C_CAL_DUMMY_PAR between CAL_DUMMY_MID and CAL_COM: PASS
4. Forbidden Capacitor Types in Calibration Bank
Checked calibration capacitors present in the project:
  • C_CAL_1K_PAR_10NF: Ceramic, Dielectric = C0G/NP0
  • C_CAL_10K_PAR_1NF: Ceramic, Dielectric = C0G/NP0
  • C_CAL_SERIES_10NF: Ceramic, Dielectric = C0G/NP0
  • C_CAL_DUMMY_PAR: Ceramic, Dielectric = C0G/NP0
No capacitor in the calibration bank was found with:
  • X7R
  • X5R
  • Y5V
  • Z5U
  • Electrolytic
  • Tantalum
Result: PASS
5. Forbidden Functional Parts Check
Schematic summary showed only:
  • Net Portal
  • Generic Resistor
  • Generic Capacitor
Not found:
  • muxes: PASS
  • electrodes: PASS
  • AD5940: PASS
  • E8: PASS
6. Exceptions / Issues Found
A. Duplicate net portal labels / extra aliases
There is only one logical net for each requested calibration net, but some nets have multiple net-portal instances attached to the same logical net. This is not an electrical short by itself, but it creates duplicate visible labels/aliases in the schematic.
Observed extra portal aliases:
  • CAL_COM has many portal instances
  • CAL_SERIES and CAL_SERIES_MID each have multiple portal instances
  • CAL_DUMMY_RC and CAL_DUMMY_MID each have multiple portal instances
  • CAL_1K_PAR_10NF is represented by portal labels named R_CAL_1K_PAR_10NF P1 - C_CAL_1K_PAR_10NF P1
  • CAL_10K_PAR_1NF is represented by portal labels named R_CAL_10K_PAR_1NF P1 - C_CAL_10K_PAR_1NF P1
Impact:
  • Logical connectivity is still correct.
  • Schematic readability is degraded.
  • These count as accidental duplicate net labels/aliases from a documentation perspective.
B. Floating-net warnings on portal pins
Electrical review reports floating pin warnings on:
  • CAL_SERIES:P1
  • CAL_SERIES_MID:P1
  • CAL_DUMMY_RC:P1
  • CAL_DUMMY_MID:P1
Interpretation:
  • These are exposed calibration nodes represented by portals.
  • Electrically they are expected to be available for later connection.
  • They are still unresolved ERC warnings at this time.
C. PCB airwires / unresolved layout connectivity
Design review reports 16 airwire errors. These are layout-level unresolved routing issues, not schematic netlist shorts.
Interpretation:
  • The schematic connectivity exists.
  • The PCB/layout side is not fully routed or synchronized for these connections.
  • This remains an unresolved review issue.
D. Manufacturing metadata gaps
Manufacturing review reports missing manufacturer part numbers on all 13 generic passives in the calibration bank.
Interpretation:
  • This does not invalidate the schematic topology.
  • It is still an unresolved manufacturing review issue.
E. Incorrect values / missing components / accidental schematic shorts
  • Incorrect values found: NONE
  • Missing requested calibration components: NONE
  • Accidental schematic shorts between distinct calibration nets: NONE found
Final Summary
Passed
  • Requested calibration nets exist
  • Requested component values are correct
  • Requested resistor/capacitor topology is correct
  • Calibration capacitors are all marked C0G/NP0
  • No muxes, electrodes, AD5940, or E8 were found
  • No accidental schematic shorts were found
Open Issues
  • Duplicate/extra net-portal labels exist on several calibration nets
  • 4 floating-pin ERC warnings on portal nodes
  • 16 PCB airwire review errors
  • 13 missing MPN manufacturing review errors
Recommendation
If the next step is cleanup, the highest-value fixes are:
  1. Remove duplicate/alias net portals so each calibration net has one intentional visible label set.
  2. Decide whether the exposed calibration nodes should remain floating or be marked intentionally for ERC handling.
  3. Resolve the PCB airwires if layout continuity matters yet.
  4. Add MPNs if you want the bank to be manufacturing-ready.
  • Overall Status

  • 1. CAL_COM / E8 Check

  • 2. Required Calibration Nets

  • 3. Component Value and Connectivity Checks

  • Simple resistor standards

  • Parallel RC standards

  • Series + parallel branch standard

  • Dummy RC placeholder network

  • 4. Forbidden Capacitor Types in Calibration Bank

  • 5. Forbidden Functional Parts Check

  • 6. Exceptions / Issues Found

  • A. Duplicate net portal labels / extra aliases

  • B. Floating-net warnings on portal pins

  • C. PCB airwires / unresolved layout connectivity

  • D. Manufacturing metadata gaps

  • E. Incorrect values / missing components / accidental schematic shorts

  • Final Summary

  • Passed

  • Open Issues

  • Recommendation