Rev A Locked Architecture Details

C

cigz75

Run AD5940 datasheet limits review only.
Do not modify schematic wiring.
Do not add components.
Do not change nets.
Review the AD5940 placeholder against datasheet/application-circuit requirements and identify what must be locked before PCB layout.
Check:
  1. Rail requirements:
  • AVDD valid voltage range
  • DVDD valid voltage range
  • IOVDD / digital I/O rail requirement
  • REG_1V8 role
  • whether DVDD_AD5940 may remain tied to MCU_3V3: yes/no/uncertain
  • whether separate 1.8 V rail placeholder is required: yes/no/uncertain
  1. SPI/logic compatibility:
  • whether STM32L552 3.3 V SPI can directly connect to AD5940: yes/no/uncertain
  • whether level shifting may be required: yes/no/uncertain
  1. BioZ/EIS pins:
  • map placeholder nets to likely AD5940 pins/functions:
    AD5940_I_PLUS_PATH
    AD5940_I_MINUS_PATH
    AD5940_V_PLUS_PATH
    AD5940_V_MINUS_PATH
    AD5940_CURRENT_SENSE_P
    AD5940_CURRENT_SENSE_N
    AD5940_EXC_MON
    AD5940_AIN_MON
  1. Application-circuit blockers:
  • required external references
  • required RTIA/RLOAD/RCAL components
  • required clock/crystal if any
  • required decoupling not already represented
  • required reset/interrupt/control pins
  1. Pre-layout decision:
    Choose one:
    A. Keep AD5940 as placeholder only
    B. Add separate 1.8 V LDO placeholder
    C. Add level-shifter placeholder only
    D. Split DVDD_AD5940 from MCU_3V3
    E. Need human datasheet review before schematic changes
Report only:
  • AD5940 rail blockers
  • SPI/logic blockers
  • missing application-circuit components
  • recommended next schematic action
  • whether current AD5940 section is safe for PCB layout: yes/no

flux

I’ll run a read-only AD5940 datasheet-limits review against the current placeholder section, check rails, SPI logic, pin-role mapping, and application-circuit gaps, then report only the blockers and next action.

flux

C

cigz75

STOP

Working through the details...

Sign up to send

Files

Schematic

Layout

3D View

USB-C Configuration: Passive 5V Sink Device
USB-C configuration for EchoS Bank Rev A:
  • J_USB_C is used for Mac/laptop USB data connection and 5 V input.
  • USB-C is configured as a passive 5 V sink/device.
  • CC1 has R_CC1 = 5.1 kΩ, 1%, 0402 to GND.
  • CC2 has R_CC2 = 5.1 kΩ, 1%, 0402 to GND.
  • No USB-C PD controller is used in Rev A.
  • No TPS25750.
  • No STUSB4500.
  • No high-voltage USB-C negotiation.
  • USB data path is: J_USB_C USB_DP/USB_DM → U_USB_ESD → USB_DP_PROTECTED/USB_DM_PROTECTED → U_MCU_STM32L552
  • USB_VBUS is routed to MCU USB_VBUS_SENSE and will later feed the protected 5 V power tree.
Rules:
  • Do not modify schematic wiring.
  • Do not add regulators.
  • Do not add PD controller.
  • Do not modify analog, mux, electrode, or calibration blocks.