Rev A Locked Architecture Details
Run AD5940 datasheet limits review only.
Do not modify schematic wiring.
Do not add components.
Do not change nets.
Review the AD5940 placeholder against datasheet/application-circuit requirements and identify what must be locked before PCB layout.
Check:
- Rail requirements:
- AVDD valid voltage range
- DVDD valid voltage range
- IOVDD / digital I/O rail requirement
- REG_1V8 role
- whether DVDD_AD5940 may remain tied to MCU_3V3: yes/no/uncertain
- whether separate 1.8 V rail placeholder is required: yes/no/uncertain
- SPI/logic compatibility:
- whether STM32L552 3.3 V SPI can directly connect to AD5940: yes/no/uncertain
- whether level shifting may be required: yes/no/uncertain
- BioZ/EIS pins:
- map placeholder nets to likely AD5940 pins/functions: AD5940_I_PLUS_PATH AD5940_I_MINUS_PATH AD5940_V_PLUS_PATH AD5940_V_MINUS_PATH AD5940_CURRENT_SENSE_P AD5940_CURRENT_SENSE_N AD5940_EXC_MON AD5940_AIN_MON
- Application-circuit blockers:
- required external references
- required RTIA/RLOAD/RCAL components
- required clock/crystal if any
- required decoupling not already represented
- required reset/interrupt/control pins
- Pre-layout decision: Choose one: A. Keep AD5940 as placeholder only B. Add separate 1.8 V LDO placeholder C. Add level-shifter placeholder only D. Split DVDD_AD5940 from MCU_3V3 E. Need human datasheet review before schematic changes
Report only:
- AD5940 rail blockers
- SPI/logic blockers
- missing application-circuit components
- recommended next schematic action
- whether current AD5940 section is safe for PCB layout: yes/no
Thought for 7 sec
I’ll run a read-only AD5940 datasheet-limits review against the current placeholder section, check rails, SPI logic, pin-role mapping, and application-circuit gaps, then report only the blockers and next action.
Worked for 1 min 10 sec
STOP
Sorry for the wait — almost done...
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MCU GPIO Assignment Draft
Draft MCU functional net assignment for EchoS Bank Rev A.
U_MCU_STM32L552 controls one AD5940 and four ADG1406-family muxes.
AD5940 SPI/control nets:
SPI_SCLK -> AD5940 SPI clock
SPI_MOSI -> AD5940 SPI MOSI
SPI_MISO -> AD5940 SPI MISO
AD5940_CS_N -> AD5940 chip select
AD5940_RST_N -> AD5940 reset
AD5940_INT_N -> AD5940 interrupt input to MCU
Mux shared address nets:
MUX_A0 -> all four mux A0 pins
MUX_A1 -> all four mux A1 pins
MUX_A2 -> all four mux A2 pins
MUX_A3 -> all four mux A3 pins
Mux independent enable nets:
MUX_I_PLUS_EN
MUX_I_MINUS_EN
MUX_V_PLUS_EN
MUX_V_MINUS_EN
Other MCU interfaces:
I2C_SCL / I2C_SDA -> temperature sensors
USB_DP / USB_DM -> USB-C device interface to Mac
AUX_ADC_IN / AUX_GPIO -> optional auxiliary header
Rules:
- This is a draft functional assignment only.
- Do not claim final STM32L552 package pins yet.
- Final GPIO package pin mapping must be checked against the selected STM32L552 package and board layout.
- Keep SPI and mux control routing away from analog sense/calibration region.
- Do not modify schematic wiring.
- Do not add components.
- Do not modify calibration bank.
- Do not modify mux map.
