Rev A Locked Architecture Details

C

cigz75

Run AD5940 datasheet limits review only.
Do not modify schematic wiring.
Do not add components.
Do not change nets.
Review the AD5940 placeholder against datasheet/application-circuit requirements and identify what must be locked before PCB layout.
Check:
  1. Rail requirements:
  • AVDD valid voltage range
  • DVDD valid voltage range
  • IOVDD / digital I/O rail requirement
  • REG_1V8 role
  • whether DVDD_AD5940 may remain tied to MCU_3V3: yes/no/uncertain
  • whether separate 1.8 V rail placeholder is required: yes/no/uncertain
  1. SPI/logic compatibility:
  • whether STM32L552 3.3 V SPI can directly connect to AD5940: yes/no/uncertain
  • whether level shifting may be required: yes/no/uncertain
  1. BioZ/EIS pins:
  • map placeholder nets to likely AD5940 pins/functions:
    AD5940_I_PLUS_PATH
    AD5940_I_MINUS_PATH
    AD5940_V_PLUS_PATH
    AD5940_V_MINUS_PATH
    AD5940_CURRENT_SENSE_P
    AD5940_CURRENT_SENSE_N
    AD5940_EXC_MON
    AD5940_AIN_MON
  1. Application-circuit blockers:
  • required external references
  • required RTIA/RLOAD/RCAL components
  • required clock/crystal if any
  • required decoupling not already represented
  • required reset/interrupt/control pins
  1. Pre-layout decision:
    Choose one:
    A. Keep AD5940 as placeholder only
    B. Add separate 1.8 V LDO placeholder
    C. Add level-shifter placeholder only
    D. Split DVDD_AD5940 from MCU_3V3
    E. Need human datasheet review before schematic changes
Report only:
  • AD5940 rail blockers
  • SPI/logic blockers
  • missing application-circuit components
  • recommended next schematic action
  • whether current AD5940 section is safe for PCB layout: yes/no

flux

I’ll run a read-only AD5940 datasheet-limits review against the current placeholder section, check rails, SPI logic, pin-role mapping, and application-circuit gaps, then report only the blockers and next action.

flux

C

cigz75

STOP

Thinking this through...

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Files

Schematic

Layout

3D View

16:1 Mux Channel Map
All four 16:1 muxes use the same IN0-IN15 map.
IN0 = E1 IN1 = E2 IN2 = E3 IN3 = E4 IN4 = E5 IN5 = E6 IN6 = E7 IN7 = CAL_COM / CAL_REF IN8 = CAL_OPEN IN9 = CAL_100R IN10 = CAL_1K IN11 = CAL_10K IN12 = CAL_1K_PAR_10NF IN13 = CAL_10K_PAR_1NF IN14 = CAL_SERIES IN15 = CAL_DUMMY_RC
Rules:
  • CAL_COM is not E8.
  • Calibration standards are pseudo-electrodes.
  • Real and calibration measurements must pass through the same mux family and same one-switch-per-terminal path.
  • Final mux part is not locked yet; ADG1406, ADG1606, ADG1206, and MUX506 remain under parasitic/metrology comparison.
  • Do not add mux components yet.
  • Do not modify the calibration bank.