Rev A Locked Architecture Details
Run AD5940 datasheet limits review only.
Do not modify schematic wiring.
Do not add components.
Do not change nets.
Review the AD5940 placeholder against datasheet/application-circuit requirements and identify what must be locked before PCB layout.
Check:
- Rail requirements:
- AVDD valid voltage range
- DVDD valid voltage range
- IOVDD / digital I/O rail requirement
- REG_1V8 role
- whether DVDD_AD5940 may remain tied to MCU_3V3: yes/no/uncertain
- whether separate 1.8 V rail placeholder is required: yes/no/uncertain
- SPI/logic compatibility:
- whether STM32L552 3.3 V SPI can directly connect to AD5940: yes/no/uncertain
- whether level shifting may be required: yes/no/uncertain
- BioZ/EIS pins:
- map placeholder nets to likely AD5940 pins/functions: AD5940_I_PLUS_PATH AD5940_I_MINUS_PATH AD5940_V_PLUS_PATH AD5940_V_MINUS_PATH AD5940_CURRENT_SENSE_P AD5940_CURRENT_SENSE_N AD5940_EXC_MON AD5940_AIN_MON
- Application-circuit blockers:
- required external references
- required RTIA/RLOAD/RCAL components
- required clock/crystal if any
- required decoupling not already represented
- required reset/interrupt/control pins
- Pre-layout decision: Choose one: A. Keep AD5940 as placeholder only B. Add separate 1.8 V LDO placeholder C. Add level-shifter placeholder only D. Split DVDD_AD5940 from MCU_3V3 E. Need human datasheet review before schematic changes
Report only:
- AD5940 rail blockers
- SPI/logic blockers
- missing application-circuit components
- recommended next schematic action
- whether current AD5940 section is safe for PCB layout: yes/no
Thought for 7 sec
I’ll run a read-only AD5940 datasheet-limits review against the current placeholder section, check rails, SPI logic, pin-role mapping, and application-circuit gaps, then report only the blockers and next action.
Worked for 1 min 10 sec
STOP
Sorry for the wait — almost done...
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Layout and Shielding Rules
EchoS Bank Rev A layout rules:
Analog region:
- Keep AD5940, HSTIA-related nets, mux COM paths, calibration bank, and electrode input paths compact.
- Keep mux COM-to-AD5940 paths short, symmetric, and guarded where practical.
- Keep calibration standards close to the mux/calibration region.
- Preserve path symmetry between live electrode measurements and internal calibration measurements.
Digital/USB region:
- Keep USB-C, ESD, CC resistors, MCU USB pins, and MCU digital switching away from AD5940 HSTIA/sense paths.
- Route USB_DP/USB_DM as controlled differential pair after final stackup review.
- Keep SPI and mux GPIO away from sensitive analog nodes where practical.
Ground/shield:
- AGND is analog/mux/calibration reference region.
- DGND is MCU/USB digital reference region.
- Do not create a bad split-plane return-current trap under analog paths.
- Final AGND/DGND connection strategy requires analog PCB engineer review.
- USB shield/chassis strategy requires enclosure/front-panel review.
Electrode dock:
- Keep E1-E8 signal paths symmetric.
- Keep guard/shield strategy consistent across all eight channels.
- Use premium keyed connector and shielded cable harness.
- Avoid cheap screw terminals for primary electrode connection.
Rules:
- Do not modify schematic wiring.
- Do not add components.
- Do not modify USB, AD5940, MCU, muxes, electrode dock, or calibration bank.
