Rev A Locked Architecture Details

C

cigz75

Run AD5940 datasheet limits review only.
Do not modify schematic wiring.
Do not add components.
Do not change nets.
Review the AD5940 placeholder against datasheet/application-circuit requirements and identify what must be locked before PCB layout.
Check:
  1. Rail requirements:
  • AVDD valid voltage range
  • DVDD valid voltage range
  • IOVDD / digital I/O rail requirement
  • REG_1V8 role
  • whether DVDD_AD5940 may remain tied to MCU_3V3: yes/no/uncertain
  • whether separate 1.8 V rail placeholder is required: yes/no/uncertain
  1. SPI/logic compatibility:
  • whether STM32L552 3.3 V SPI can directly connect to AD5940: yes/no/uncertain
  • whether level shifting may be required: yes/no/uncertain
  1. BioZ/EIS pins:
  • map placeholder nets to likely AD5940 pins/functions:
    AD5940_I_PLUS_PATH
    AD5940_I_MINUS_PATH
    AD5940_V_PLUS_PATH
    AD5940_V_MINUS_PATH
    AD5940_CURRENT_SENSE_P
    AD5940_CURRENT_SENSE_N
    AD5940_EXC_MON
    AD5940_AIN_MON
  1. Application-circuit blockers:
  • required external references
  • required RTIA/RLOAD/RCAL components
  • required clock/crystal if any
  • required decoupling not already represented
  • required reset/interrupt/control pins
  1. Pre-layout decision:
    Choose one:
    A. Keep AD5940 as placeholder only
    B. Add separate 1.8 V LDO placeholder
    C. Add level-shifter placeholder only
    D. Split DVDD_AD5940 from MCU_3V3
    E. Need human datasheet review before schematic changes
Report only:
  • AD5940 rail blockers
  • SPI/logic blockers
  • missing application-circuit components
  • recommended next schematic action
  • whether current AD5940 section is safe for PCB layout: yes/no

flux

I’ll run a read-only AD5940 datasheet-limits review against the current placeholder section, check rails, SPI logic, pin-role mapping, and application-circuit gaps, then report only the blockers and next action.

flux

C

cigz75

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Schematic

Layout

3D View

Mux Part Selection Pending
The final 16:1 mux part is not locked yet.
Candidate muxes under metrology comparison:
  • ADG1206
  • ADG1406
  • ADG1606
  • TI MUX506
Selection must be based on best total metrology behavior after same-path calibration, not lowest Ron alone.
Compare:
  • Ron typical and maximum
  • Ron flatness
  • Ron matching
  • on capacitance
  • off capacitance
  • charge injection
  • on leakage
  • off leakage
  • off isolation
  • channel-to-channel crosstalk
  • bandwidth
  • package
  • supply rails
  • expected phase error at 100 Ω, 1 kΩ, and 10 kΩ from 1 kHz to 500 kHz
Rules:
  • Do not lock ADG1606 just because it has low Ron.
  • Do not reject ADG1206 only because of high Ron without documented calculation.
  • Preserve path symmetry and same-path calibration.
  • Four muxes must be identical.
  • All muxes must use the same IN0-IN15 channel map already documented.
  • Do not add mux components yet.
  • Do not modify the calibration bank.