Rev A Locked Architecture Details
Run AD5940 datasheet limits review only.
Do not modify schematic wiring.
Do not add components.
Do not change nets.
Review the AD5940 placeholder against datasheet/application-circuit requirements and identify what must be locked before PCB layout.
Check:
- Rail requirements:
- AVDD valid voltage range
- DVDD valid voltage range
- IOVDD / digital I/O rail requirement
- REG_1V8 role
- whether DVDD_AD5940 may remain tied to MCU_3V3: yes/no/uncertain
- whether separate 1.8 V rail placeholder is required: yes/no/uncertain
- SPI/logic compatibility:
- whether STM32L552 3.3 V SPI can directly connect to AD5940: yes/no/uncertain
- whether level shifting may be required: yes/no/uncertain
- BioZ/EIS pins:
- map placeholder nets to likely AD5940 pins/functions: AD5940_I_PLUS_PATH AD5940_I_MINUS_PATH AD5940_V_PLUS_PATH AD5940_V_MINUS_PATH AD5940_CURRENT_SENSE_P AD5940_CURRENT_SENSE_N AD5940_EXC_MON AD5940_AIN_MON
- Application-circuit blockers:
- required external references
- required RTIA/RLOAD/RCAL components
- required clock/crystal if any
- required decoupling not already represented
- required reset/interrupt/control pins
- Pre-layout decision: Choose one: A. Keep AD5940 as placeholder only B. Add separate 1.8 V LDO placeholder C. Add level-shifter placeholder only D. Split DVDD_AD5940 from MCU_3V3 E. Need human datasheet review before schematic changes
Report only:
- AD5940 rail blockers
- SPI/logic blockers
- missing application-circuit components
- recommended next schematic action
- whether current AD5940 section is safe for PCB layout: yes/no
Thought for 7 sec
I’ll run a read-only AD5940 datasheet-limits review against the current placeholder section, check rails, SPI logic, pin-role mapping, and application-circuit gaps, then report only the blockers and next action.
Worked for 1 min 10 sec
STOP
Sorry for the wait — almost done...
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Final Rev A Planning Skeleton Summary
EchoS Bank Rev A planning skeleton summary:
Core architecture:
- 8 live external electrode inputs: E1-E8.
- Four ADG1406-family 16:1 mux placeholders.
- One AD5940 functional placeholder.
- One STM32L552 MCU placeholder.
- USB-C to Mac/laptop for data and 5 V input.
- Passive USB-C 5 V sink/device mode.
- Internal calibration bank on mux IN8-IN15.
Mux map:
- IN0-IN7 = E1-E8.
- IN8 = CAL_OPEN.
- IN9 = CAL_SHORT.
- IN10 = CAL_100R.
- IN11 = CAL_1K.
- IN12 = CAL_10K.
- IN13 = CAL_1K_PAR_10NF.
- IN14 = CAL_10K_PAR_1NF.
- IN15 = CAL_SERIES.
Calibration:
- CAL_COM/CAL_REF is internal only.
- CAL_COM is not E8.
- CAL_SHORT is 0 Ω to CAL_COM.
- Calibration standards are pseudo-electrodes.
- Live and calibration measurements use the same mux path principle.
USB/power:
- J_USB_C default candidate: Würth Elektronik 632723300011.
- Backup USB-C candidate: Amphenol 12401610E4#2A.
- USB data passes through U_USB_ESD before MCU.
- CC1/CC2 use 5.1 kΩ pull-downs to GND.
- USB_VBUS feeds U_USB_POWER_PROTECTION then 5V_PROTECTED.
- Digital LDO placeholder feeds DVDD_AD5940 / MCU_3V3.
- Analog LDO placeholder feeds AVDD_AD5940.
- AVDD_AD5940 remains separate from DVDD_AD5940 / MCU_3V3.
Status:
- Real schematic issues requiring correction: 0 detected.
- Remaining ERC/DRC issues are placeholder/manufacturing-readiness issues.
- This is ready for PCB-engineer datasheet review.
- This is not yet manufacturing-ready.
Rules:
- Do not modify schematic wiring.
- Do not add components.
- Do not change nets.
