FPGA vs Microcontroller vs ASIC: A Design Guide

Quick answer

• Microcontroller (MCU): Choose an MCU for motor control when its peripherals suffice, and for low-power wearables that spend much of their time asleep.
• Field-programmable gate array (FPGA): Choose an FPGA for high-speed analog-to-digital converter (ADC) capture, digital signal processing (DSP), concurrent video/camera processing beyond MCU capabilities, or digital custom-chip prototyping.
• Complex programmable logic device (CPLD): Choose a CPLD for compact custom logic, or an FPGA for larger custom protocols.
• Application-specific integrated circuit (ASIC): Choose an ASIC for a stable function and validated lifetime business case.
• Hybrid: Choose an MCU-plus-FPGA or system-on-chip (SoC) FPGA when control and acceleration are both needed.

MCU vs FPGA vs ASIC at a glance

The table compares execution, timing, development cost, power and PCB needs across MCU, FPGA and ASIC architectures. Peripheral capabilities and configuration behavior vary by device, so check the manufacturer references below. [S1–S6]

What actually runs in parallel?

A CPU executes instruction streams, and an MCU contains a CPU alongside dedicated peripherals. Timers, converters, direct memory access (DMA) controllers and peripheral interconnects can operate independently of the CPU core. For example, STMicroelectronics' STM32G431 supports autonomous peripheral connections with predictable latency. [S1]

Raspberry Pi's RP2350 MCU adds multicore processing and programmable input/output (PIO) state machines. PIO can implement custom interfaces without an FPGA, but PIO has fixed state-machine and instruction limits. [S2]

FPGA register-transfer level (RTL) code describes hardware that synthesis maps into logic, registers, memories and routing. Independent instantiated paths operate concurrently. Pipelining allows successive data items to occupy different processing stages simultaneously. More throughput does not automatically mean less end-to-end latency, because buffering, pipeline stages and backpressure still count. [S5]

Deterministic timing means meeting a specified input-to-output deadline. An FPGA still needs clock-domain-crossing controls, reliable reset behavior, complete timing constraints and bounded buffering. Likewise, an MCU using timer-triggered capture and DMA may be more appropriate than interrupt-driven software pin toggling (bit-banging). Establish the actual deadline before comparing architectures. [S1, S2, S5]

Choose an MCU if…

• The required motor-control signals fit the MCU's PWM timers, synchronized acquisition and protection paths. For example, STM32G431's motor-control timers support several control functions, subject to the selected motor driver's needs. [S1]
• A low-power wearable spends much of its life asleep and only occasionally samples, computes, or communicates. Validate the selected part's wake behavior and the whole board's leakage. [S1, S2]
• The product mainly manages sensors, user interfaces, control state, and established serial buses.
• Requirements change frequently and firmware can absorb the changes without new interfaces.
• DMA and integrated peripherals meet acquisition throughput and memory deadlines without overruns.

Start with a peripheral allocation and memory-transfer budget. If the selected MCU meets both, an FPGA may add unnecessary configuration, hardware description language (HDL) and supply work. For family context, see Flux's STM32 microcontroller guide. Use the manufacturer's documents for electrical decisions.

Choose an FPGA if…

• High-speed ADC capture requires simultaneous lanes, buffering, or DSP beyond a proven MCU acquisition path.
• Video or camera processing needs concurrent pixel pipelines or interfaces absent from the MCU. Confirm interface IP, memory bandwidth, and package support before choosing a specific FPGA.
• A custom interface requires more precisely timed signals, parallel channels or buffering than the MCU peripherals and PIO can provide.
• The design needs reconfigurable glue, bridges, or accelerators whose hardware architecture will evolve.
• The project prototypes digital ASIC behavior and needs repeatable hardware execution before committing to silicon.

The exact FPGA must have enough logic, suitable I/O standards and verified timing for the intended workload. [S3, S5]

Choose an ASIC if…

ASIC development requires extensive verification, fabrication and production-test resources.

• The function is stable enough that hardware changes can be managed through a new silicon revision.
• A verified custom architecture solves an integration or workload-efficiency problem unavailable off the shelf.
• Lifetime system-cost savings justify development, IP, manufacturing, package, test, and validation commitments.
• The business can support silicon verification, physical signoff, production-test development, and manufacturing ownership.
• The application needs custom analog/digital integration and the process/IP choices have been validated.

ASIC means custom silicon here. A component-library entry cannot verify a proposed custom chip. Altera's historical HardCopy structured-ASIC methodology describes equivalence checking, test insertion, timing closure, design-rule checking (DRC) and layout-versus-schematic checking (LVS). Current fabrication still requires process-specific verification. [S6]

Cost, field updates, and the million-unit question

To estimate when ASIC development becomes economical, compare fixed engineering costs with the cost of each shipped unit:

$${\mathrm{Total}}_A(N)=F_A+N\times U_A$$

$${\mathrm{Total}}_B(N)=F_B+N\times U_B$$

$$N_{\text{break-even}}=\frac{F_A-F_B}{U_B-U_A}$$

N is the number of units. F includes nonrecurring project costs, and U includes delivered system cost per unit. If A costs more to develop but less per unit than B, the positive break-even volume shows when A becomes cheaper. The equations do not predict semiconductor prices.

Include support bill-of-materials (BOM) parts, PCB fabrication, assembly, programming, test, yield-related costs, licensing and maintenance in the totals for both options. Treat uncertainty and silicon-respin exposure as separate cost scenarios. FPGA projects also have nonrecurring engineering expenses even without ASIC mask charges.

Production volume alone does not determine the architecture. A consumer product at 1 million units is not automatically an ASIC candidate. For example, a stable accelerator with defensible quoted system savings may justify custom silicon, whereas a changing product whose inexpensive MCU already meets requirements may not. Compare lifetime shipments, product variants and the cost of losing hardware reconfigurability before committing. [S6, S8]

MCU firmware and supported FPGA configurations can be field-updated, subject to boot, security, recovery, and memory design. ASIC circuitry stays fixed, but an ASIC containing a processor or programmable blocks may still accept software updates. Design and test the update, rollback and recovery circuits rather than treating field updates as a software-only feature. [S1–S3]

Design considerations: schematic, BOM, and PCB

Board-level power, memory and layout requirements vary by architecture.

Power rails and sequence. List every supply domain and its startup, ramp and shutdown requirements from the exact device documentation. For example, Lattice's iCE40 UltraPlus FPGA has core, phase-locked-loop (PLL), bank/configuration and nonvolatile configuration memory (NVCM) supplies. Follow the specific device's power-up sequence. MCU analog, backup, regulator and I/O supplies may also be separate. [S1, S3]

Configuration memory. Many SRAM FPGAs load configuration from external flash or a host. Small nonvolatile/flash-based alternatives can change the BOM. iCE40 UltraPlus supports NVCM and serial peripheral interface (SPI) configuration. NVCM has different write limits from updateable flash. The RP2350A MCU also needs external program flash. [S2, S3]

JTAG and debug. Reserve programming access, ground, target-voltage reference, reset/status access and a production fixture for programming and testing. Use the selected chip's interface: the iCE40 example uses SPI configuration, whereas the CPLD exposes JTAG signals TCK, TMS, TDI and TDO. STM32G431 supports serial wire debug (SWD) or JTAG. [S1, S3, S4]

Clocks. For MCUs, FPGAs and ASICs, choose clock sources from interface accuracy, jitter, startup and timing needs. Internal oscillators can simplify a board but may not meet external interface requirements. Map external clocks to suitable pins and apply timing constraints where required. [S2, S3, S5]

BGA fanout and layers. Package choice, used pins, escape geometry, return paths, power distribution and fabrication capabilities determine the stackup. Package selection matters: the iCE40 example uses a quad flat no-lead (QFN) package, while the CPLD uses a ball-grid array (BGA) whose pins may require extra vias or routing layers. [S3, S4]

Decoupling and I/O banks. Follow the selected device's supply and PCB guidance. Then validate the workload's power distribution. Assign bank voltages before finalizing pin placement, check every connected interface and include level translation when required. Do not assume mixed-voltage signals can share a bank simply because the symbol has spare pins. AMD's power-distribution guidance ties decoupling validation to design activity and assumptions. See Flux's PCB power distribution guide. [S3, S4, S7]

Dynamic versus static power. Static consumption persists without useful switching, whereas dynamic consumption depends on clocks, toggling, memory and I/O activity. Therefore, compare sleep-heavy and continuously streaming workloads separately, including regulators and external memory. An FPGA pipeline or custom ASIC may consume less energy for a specific workload, but the result requires a measured comparison. [S7]

Tools, learning curve, and hybrid architectures

Tools affect development effort.

MCU work usually means C/C++, compiler/linker tools, drivers, and debugger-based firmware validation. FPGA work usually means Verilog/VHDL, testbenches, simulation, synthesis, place-and-route, and timing closure. High-level synthesis can generate RTL from C++-style code, but the generated circuits still require timing and interface verification. Compare the team's firmware and hardware-design skills before selecting tools. [S5]

Tool licenses also affect engineering cost. Check current device support and license terms before freezing the BOM. Free tool tiers or included simulators may exclude particular devices, IP blocks or verification features. Budget commercial IP and team training separately. ASIC work additionally requires process-specific implementation and verification/signoff resources. [S5, S6, S8]

For systems needing software control and parallel acceleration, SoC FPGAs combine hard processors with programmable fabric. An MCU-plus-FPGA board achieves a related partition using separate parts: firmware handles management while fabric handles acquisition or acceleration. Allow for communication between chips, buffering, startup coordination and separate programming paths. [S5, S7]

Minimal reference circuit descriptions

The following schematic starting points show how power, clocks, configuration and programming differ across architectures. The examples have not been electrically reviewed. Regulators, flash, clocks, connectors, passive values, protection and load interfaces require part-specific selection. Obtain exact requirements from the sources before implementation.

MCU: STM32G431CBU6, STMicroelectronics. To supply and program the MCU, follow DS12589 Rev 6 supply, pinout and debug sections. Connect all supply/ground functions, analog/reference and backup supplies. Also expose SWDIO/SWCLK, reset and target reference, and set boot/reset behavior. Embedded flash removes separate program flash. Check the complete manufacturer reference circuit. [S1]

MCU exception: RP2350A, Raspberry Pi. Follow Hardware design with RP2350, Release 3, for the minimal-board circuit and external-flash connections. Connect the regulator's external energy-storage and feedback network to VREG_LX/VREG_FB, QSPI signals to compatible external flash and XIN/XOUT clock circuitry. Expose SWD, RUN/reset and boot-selection access. Use the manufacturer's complete circuit and values. [S2]

For details about silicon revisions, see Flux's RP2350 A4 stepping article. Confirm the supplied revision separately.

FPGA: ICE40UP5K-SG48I, Lattice Semiconductor. For the FPGA, follow FPGA-DS-02008 Rev 2.4 supply, configuration and pin-function sections. Connect VCC/VCCPLL, VPP_2V5, bank supplies and grounds. Select controller-mode SPI flash or a host-driven peripheral-mode SPI path. Then expose CRESET_B and CDONE, and provide a suitable clock. Follow the documented supply order and configuration-pin behavior. [S3]

CPLD: LC4032ZE-4MN64C, Lattice Semiconductor. For compact control logic, use DS1022 Rev 1.9 package-specific pin tables and in-system programming (ISP) sections. Connect VCC, VCCO bank supplies and grounds. Expose TCK/TMS/TDI/TDO with a programmer compatible with the core-referenced interface. Then connect the application clock and required glue signals. The macrocell-based example is suited to evaluating decoding/state-machine glue rather than an FPGA's larger DSP datapath. [S4]

ASIC architecture template. For a custom chip, define package/pad ring, core/I/O supplies, reset/clocks, test access, memory and application ports from the custom specification. Select regulators, decoupling, clocks and test connections only after silicon/package requirements exist. The result is an architecture checklist rather than a finished circuit. FPGA prototyping cannot replace process-specific timing, physical, analog or test signoff. [S6, S8]

FAQ

FPGA vs microcontroller: which should I choose first?

Is an FPGA faster than an MCU?

CPLD vs FPGA: where does a CPLD fit?

FPGA vs ASIC: when does ASIC become cheaper?

Can an MCU replace an FPGA for custom protocols?

Can I update an ASIC like an FPGA?

Sources and library verification

• S1: STMicroelectronics, STM32G431x6/x8/xB datasheet, DS12589 Rev 6, October 2021. Supply, flash, DMA, timers, interconnect, and debug sections.
• S2: Raspberry Pi, Hardware design with RP2350, Release 3, build 20/08/2026, 06a7f75e58a1. Official RP2350 documentation,
• S3: Lattice Semiconductor, iCE40 UltraPlus Family Data Sheet, FPGA-DS-02008 Rev 2.4, February 2025.
• S4: Lattice Semiconductor, ispMACH 4000ZE Family Data Sheet DS1022 Rev 1.9, October 2015, official downloads.
• S5: Intel, oneAPI FPGA Development Flow, 2024.1. AMD, Vivado Verification.
• S6: Altera, Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis/Timing Constraints, WP-01095-1.2, February 2009. Historical structured-ASIC methodology used only for verification concepts, not present-day cost or availability.
• S7: AMD, Power Analysis and Optimization UG907, 2024.2. Power Distribution System, UG949, 2025.2. Device-specific guidance, not universal rail or capacitor values.
• S8: Intel Foundry, Accelerator design ecosystem. Process-specific IP, EDA, and specification-to-silicon services.