RF Board Connection Adaptation

IPC-2581C exported successfully as a file, so I’ll wrap it into a ZIP. DXF export failed once; I’m retrying DXF before packaging.
DXF exported successfully as a ZIP. I’m wrapping the IPC-2581C file into its own ZIP now.
The zip wrapper tool didn’t receive the IPC attachment automatically, so I’m doing one direct download-and-zip attempt from the signed IPC-2581C URL.
DXF ZIP is ready:
IPC-2581C exported successfully, but Flux produced it as a single .ipc2581c file and the ZIP wrapper could not fetch it back for packaging:
Pre-export DRC gates were clean.
Package and verify exports
Export ODB++ too
Export STEP model
Check package contents
Create fab email
J2
J3
R_I2C_SDA
Resistance
2.2kΩ
R_LNA0
Resistance
10kΩ
R_SOC_GPIO_JMP
Resistance
R_CLKREQ
Resistance
1kΩ
R_LNA2
Resistance
10kΩ
R_WAKE
Resistance
10kΩ
R_I2C_SCL
Resistance
2.2kΩ
R_Y1
Resistance
33Ω
R_SOC_PERST_JMP
Resistance
R_WLAN_DIS
Resistance
10kΩ
R_SOC_PU
Resistance
10kΩ
R_LNA3
Resistance
10kΩ
J4
J1
C_BULK1
End of Life
Capacitance
100µF
C_AC_RX0_P
Capacitance
220nF
C_BULK2
Capacitance
22µF
C_AC_RX0_N
Capacitance
220nF
C_AC_TX1_P
Capacitance
220nF
C_AC_TX1_N
Capacitance
220nF
C_AC_RX1_P
Capacitance
220nF
C_AC_TX0_N
Capacitance
220nF
C_BULK3
Capacitance
1µF
C_AC_TX0_P
Capacitance
220nF
C_AC_RX1_N
Capacitance
220nF
C_SOC_RST
Capacitance
1µF
Y1
J5

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Routing Pass Status
Date: 2026-07-16
Summary
  • Continued PCB routing from the placed 6-layer adapter layout.
  • Autoroute completed successfully and applied 591 routing nodes.
  • Normalized route segment trace widths to 0.15 mm after one route-check failure reported an invalid/too-small wire width.
  • Removed congested GND routing only, then rebuilt key connector GND stitching manually with targeted routes.
  • Signal-integrity checks queried after routing showed no open impedance, differential-pair, differential-via-pair, electrical-length, via-transition, DFM edge-clearance, or plane-coverage warnings/errors matching the selected review set.
Current DRC Status
Open DRC remains limited to 4 GND airwires:

Table


CheckUnresolved endpointsNotes
20J1:20 ↔ J1:24Direct route blocked. J1:20 was tied to J1:19, but the checker still reports the direct airwire to J1:24.
401437a5GND stitch via ↔ J2:GND_15Stitch via remains disconnected from J2:GND_15.
GND_65J2:GND_65 ↔ J2:GND_67Direct route blocked. J2:GND_65 was tied to J2:GND_63, but the checker still reports the direct pair.
GND_76J2:GND_76 ↔ J2:GND_74Direct route blocked. J2:GND_76 was tied to J2:GND_78, but the checker still reports the direct pair.
Completed GND Surgical Routes
  • J1:10 ↔ J1:13 routed.
  • J1:20 ↔ J1:19 routed as an alternate local tie.
  • J2:GND_38 ↔ J2:GND_36 routed.
  • J2:GND_20 ↔ J2:GND_18 routed.
  • J2:GND_32 ↔ J2:GND_30 routed.
  • J2:GND_26 ↔ J2:GND_24 routed.
  • J2:GND_44 ↔ J2:GND_42 routed.
  • J2:GND_65 ↔ J2:GND_63 routed as an alternate local tie.
  • J2:GND_76 ↔ J2:GND_78 routed as an alternate local tie.
  1. Inspect the remaining four GND airwires visually around J1 and J2.
  2. Consider small local placement/routing relief around J1:24 and the J2 outer GND pad groups, or add explicit GND copper/plane connections if the fabrication flow supports them.
  3. Re-run full DRC after those ground-airwire fixes.
  4. Confirm high-speed route quality visually, especially PCIe/refclock pair symmetry and via counts, before manufacturing export.
  • Summary

  • Current DRC Status

  • Completed GND Surgical Routes

  • Recommended Next Actions

RF Board Adapter Draft thumbnail
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Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

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$1.59–$2.48

Digi-Key

$0.74

HQonline

$0.44

LCSC

$3.97–$5.28

Mouser

$4.52

TME

$0.98

Verical

$1.90–$80.73

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