RF Board Connection Adaptation
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IPC-2581C exported successfully as a file, so I’ll wrap it into a ZIP. DXF export failed once; I’m retrying DXF before packaging.
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DXF exported successfully as a ZIP. I’m wrapping the IPC-2581C file into its own ZIP now.
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The zip wrapper tool didn’t receive the IPC attachment automatically, so I’m doing one direct download-and-zip attempt from the signed IPC-2581C URL.
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DXF ZIP is ready:
IPC-2581C exported successfully, but Flux produced it as a single
.ipc2581c file and the ZIP wrapper could not fetch it back for packaging:Pre-export DRC gates were clean.
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Preliminary RF Adapter Map
Date: 2026-07-07
Scope
Draft adapter mapping between:
- PCB220C / N367 / WiGig BU360 baseband/main board — based on readable schematic PDF plus assembly/silkscreen PDFs.
- PC-0705-1 / VZ-T260-FR2 RF-side board — based on readable IPC/EMN extraction and BOM/mechanical data.
This is preliminary because the PCB220C connector pin-to-net table for J4/J5/J12/J13 is still unavailable. The map below is therefore function-level, not fabrication-ready pin-level on the PCB220C side.
Available Evidence
PCB220C Evidence
Readable files show:
- RF/modem interface uses multiple 26-pin FPC connectors, visible on silkscreen/assembly as J4, J5, J12, J13 with LEFT/RIGHT orientation markings and visible pin numbers including 1, 2, 26.
- Schematic page labelled MODEM / WiGig MODEM shows FPC signal groups:
- PCIe ports 0–3 lanes/refclocks
- Reset / disable / exist signals
- TimePulse signals
- 3V3 and GND
- The schematic text indicates controlled impedance classes:
- PCIe-like high-speed differential pairs: typically 85 Ω differential
- Some clock/diff groups: 100 Ω differential
PC-0705-1 Evidence
Readable IPC/EMN data shows:
- Main interface connector: JP2 = SK2X40-ST-08-B, 80-pin board-to-board connector.
- JP2 carries:
- PCIe x2
- PCIe REFCLK
- WK_REFCLK_0/1
- I2C_B2B
- WSI clock/data
- Reset / wake / CLKREQ
- LNA enable
- 3V3 and GND
PC-0705-1 JP2 Pin Map — Extracted
Table
| JP2 Pin | Net | Confidence |
|---|---|---|
| 1 | Unknown | Not found in IPC extraction |
| 2 | GND | High |
| 3 | GND | High |
| 4 | I2C_SCL_B2B | High |
| 5 | PCIE_CLKREQ_N | High |
| 6 | I2C_SDA_B2B | High |
| 7 | Unknown | Not found in IPC extraction |
| 8 | GND | High |
| 9 | Unknown | Not found in IPC extraction |
| 10 | WSI_CLK_IN | High |
| 11 | WK_REFCLK_1_P | High |
| 12 | WSI_DATA_IN | High |
| 13 | WK_REFCLK_1_N | High |
| 14 | LNA_EN_CH0 | High |
| 15 | GND | High |
| 16 | PCI_WAKE_N_R | High |
| 17 | PCIE_RX1_N | High |
| 18 | GND | High |
| 19 | PCIE_RX1_P | High |
| 20 | GND | High |
| 21 | GND | High |
| 22 | SOC_RST_R | High |
| 23 | PCIE_TX1_N | High |
| 24 | GND | High |
| 25 | PCIE_TX1_P | High |
| 26 | GND | High |
| 27 | GND | High |
| 28 | SPARE2 | High |
| 29 | PCIE_REFCLK_N | High |
| 30 | GND | High |
| 31 | PCIE_REFCLK_P | High |
| 32 | GND | High |
| 33 | GND | High |
| 34 | m0019 | High name extraction, low functional meaning |
| 35 | PCIE_RX0_N | High |
| 36 | GND | High |
| 37 | PCIE_RX0_P | High |
| 38 | GND | High |
| 39 | GND | High |
| 40 | PCIE_RESETN_R | High |
| 41 | PCIE_TX0_N | High |
| 42 | GND | High |
| 43 | PCIE_TX0_P | High |
| 44 | GND | High |
| 45 | GND | High |
| 46 | SPARE3 | Medium; net name seen but no full line detail |
| 47 | m0016 | High name extraction, low functional meaning |
| 48 | GND | High |
| 49 | GND | High |
| 50 | GND | High |
| 51 | GND | High |
| 52 | WSI_DATA_OUT | High |
| 53 | GND | High |
| 54 | WSI_CLK_OUT | High |
| 55 | WK_REFCLK_0_N | High |
| 56 | GND | High |
| 57 | WK_REFCLK_0_P | High |
| 58 | GND | High |
| 59 | 3V3 or Unknown | Inferred from surrounding power-bank pattern; verify |
| 60 | GND | High |
| 61 | 3V3 | High |
| 62 | 3V3 | High |
| 63 | 3V3 or Unknown | Inferred from power-bank pattern; verify |
| 64 | 3V3 | High |
| 65 | 3V3 or Unknown | Inferred from power-bank pattern; verify |
| 66 | 3V3 | High |
| 67 | 3V3 or Unknown | Inferred from power-bank pattern; verify |
| 68 | 3V3 | High |
| 69 | 3V3 | High |
| 70 | 3V3 | High |
| 71 | 3V3 | High |
| 72 | 3V3 | High |
| 73 | 3V3 | High |
| 74 | GND | High |
| 75 | 3V3 | High |
| 76 | GND | High |
| 77 | 3V3 | High |
| 78 | GND | High |
| 79 | 3V3 | High |
| 80 | GND | High |
PCB220C Signal Groups — Extracted Functionally
The readable schematic shows these modem/FPC interface nets, but not exact connector pin numbers:
Port 0 / Port 1 Group
- PCIE0_L0_RXP / PCIE0_L0_RXN
- PCIE0_L0_TXP / PCIE0_L0_TXN
- PCIE0_REFCLKP / PCIE0_REFCLKN
- PCIE0_L1_RXP / PCIE0_L1_RXN
- PCIE0_L1_TXP / PCIE0_L1_TXN
- PCIE1_RXP / PCIE1_RXN
- PCIE1_TXP / PCIE1_TXN
- PCIE1_REFCLKP / PCIE1_REFCLKN
- PCIe0_Disable_n / PCIe1_Disable_n
- PCIe0_RST_n / PCIe1_RST_n
- Port0_Exist / Port1_Exist
- TimePulse0 / TimePulse1
- TimePulse0_from_M2 / TimePulse1_from_M2
- 3V3 / GND
Port 2 / Port 3 Group
- PCIE2_L0_RXP / PCIE2_L0_RXN
- PCIE2_L0_TXP / PCIE2_L0_TXN
- PCIE2_L1_RXP / PCIE2_L1_RXN
- PCIE2_L1_TXP / PCIE2_L1_TXN
- PCIE2_REFCLKP / PCIE2_REFCLKN
- PCIE3_RXP / PCIE3_RXN
- PCIE3_TXP / PCIE3_TXN
- PCIE3_REFCLKP / PCIE3_REFCLKN
- PCIe2_Disable_n / PCIe3_Disable_n
- PCIe2_RST_n / PCIe3_RST_n
- Port2_Exist / Port3_Exist
- TimePulse2 / TimePulse3
- TimePulse2_from_M2 / TimePulse3_from_M2
- 3V3 / GND
Preliminary Adapter Mapping — Function Level
Assumption for this draft: PCB220C is the host/baseband side and PC-0705-1 JP2 is the RF module side. Therefore PCIe TX/RX must be crossed: host TX → module RX, and module TX → host RX.
Candidate Lane Mapping: Use PCB220C Port 0 → PC-0705-1 JP2 PCIe Lane 0
Table
| Function | PCB220C Signal | PC-0705-1 JP2 Signal/Pin | Adapter Action | Risk |
|---|---|---|---|---|
| PCIe lane 0 host TX+ | PCIE0_L0_TXP | JP2 pin 37 / PCIE_RX0_P | Cross TX→RX | Verify naming reference direction |
| PCIe lane 0 host TX- | PCIE0_L0_TXN | JP2 pin 35 / PCIE_RX0_N | Cross TX→RX | Verify polarity and endpoint naming |
| PCIe lane 0 host RX+ | PCIE0_L0_RXP | JP2 pin 43 / PCIE_TX0_P | Cross RX←TX | Verify naming reference direction |
| PCIe lane 0 host RX- | PCIE0_L0_RXN | JP2 pin 41 / PCIE_TX0_N | Cross RX←TX | Verify polarity and endpoint naming |
| PCIe refclk + | PCIE0_REFCLKP | JP2 pin 31 / PCIE_REFCLK_P | Same polarity | Verify source direction and common-clock/SRNS mode |
| PCIe refclk - | PCIE0_REFCLKN | JP2 pin 29 / PCIE_REFCLK_N | Same polarity | Verify source direction and AC coupling placement |
| PCIe reset | PCIe0_RST_n or PCIE0_PERST_n | JP2 pin 40 / PCIE_RESETN_R | Direct active-low reset | Verify voltage and reset timing |
| PCIe CLKREQ# | If available on PCB220C | JP2 pin 5 / PCIE_CLKREQ_N | Direct if used | PCB220C schematic did not expose exact matching net in readable text |
| PCIe WAKE# | If available on PCB220C | JP2 pin 16 / PCI_WAKE_N_R | Direct if used | PCB220C readable text did not expose WAKE# |
| Module present / exist | Port0_Exist or WG0_Exist_n | No clear JP2 equivalent found | Probably strap or leave per firmware need | High risk: polarity and pull-up/down unknown |
| Module disable | PCIe0_Disable_n or WG0_DISABLE_n | No clear JP2 equivalent found | Needs logic review | High risk: may block enumeration if wrong |
| 3.3 V power | 3V3 | JP2 pins 61,62,64,66,68–73,75,77,79 plus likely 59/63/65/67 | Parallel power pins | Verify current, sequencing, and inrush |
| Ground | GND | JP2 many pins including 2,3,8,15,18,20,21,24,26,27,30,32,33,36,38,39,42,44,45,48–51,53,56,58,60,74,76,78,80 | Preserve ground pin adjacency | Critical for PCIe SI |
Optional / Secondary Lane Mapping: PCB220C Port 1 → PC-0705-1 JP2 PCIe Lane 1
Table
| Function | PCB220C Signal | PC-0705-1 JP2 Signal/Pin | Adapter Action | Risk |
|---|---|---|---|---|
| PCIe lane 1 host TX+ | PCIE1_TXP or PCIE0_L1_TXP | JP2 pin 19 / PCIE_RX1_P | Cross TX→RX | Need determine whether PC-0705-1 expects lane 1 as same PCIe link or separate link |
| PCIe lane 1 host TX- | PCIE1_TXN or PCIE0_L1_TXN | JP2 pin 17 / PCIE_RX1_N | Cross TX→RX | Same risk |
| PCIe lane 1 host RX+ | PCIE1_RXP or PCIE0_L1_RXP | JP2 pin 25 / PCIE_TX1_P | Cross RX←TX | Same risk |
| PCIe lane 1 host RX- | PCIE1_RXN or PCIE0_L1_RXN | JP2 pin 23 / PCIE_TX1_N | Cross RX←TX | Same risk |
| Refclk lane/link 1 | PCIE1_REFCLKP/N if independent | JP2 PCIE_REFCLK pins 31/29 or WK_REFCLK_1 pins 11/13 | Do not connect until clock architecture is confirmed | High risk: JP2 has both PCIE_REFCLK and WK_REFCLK_1 |
Non-PCIe / Control Mapping Candidates
Table
| Function | PCB220C Candidate | PC-0705-1 JP2 Candidate | Recommendation | Risk |
|---|---|---|---|---|
| I2C SCL | CP0_I2C0_SCK or I2C_SCL | JP2 pin 4 / I2C_SCL_B2B | Direct if both 3.3 V | Verify pull-ups and address conflicts |
| I2C SDA | CP0_I2C0_SDA or I2C_SDA | JP2 pin 6 / I2C_SDA_B2B | Direct if both 3.3 V | Verify pull-ups and address conflicts |
| Time pulse to RF | TimePulse0/1/2/3 | WSI_CLK_IN / WSI_DATA_IN or no direct match | Do not connect blindly | High risk: WSI is not necessarily TimePulse |
| Time pulse from RF | TimePulse*_from_M2 | WSI_CLK_OUT / WSI_DATA_OUT or no direct match | Do not connect blindly | High risk: direction/function unknown |
| WK reference clock 0 | No exact PCB220C match; maybe WiGig clock/ref | JP2 pins 57/55 / WK_REFCLK_0_P/N | Leave unconnected until clock requirement confirmed | High risk |
| WK reference clock 1 | No exact PCB220C match; maybe WiGig clock/ref | JP2 pins 11/13 / WK_REFCLK_1_P/N | Leave unconnected until clock requirement confirmed | High risk |
| LNA enable | RF enable / WG enable candidate | JP2 pin 14 / LNA_EN_CH0 | Needs polarity and voltage verification | High risk if wrong |
| SOC reset | Main reset / module reset candidate | JP2 pin 22 / SOC_RST_R | Needs sequencing review | High risk |
| Spare/internal | SPARE2, SPARE3, m0016, m0019 | JP2 pins 28,46,47,34 | Leave DNP / test pads | Unknown function |
Mechanical / Connector Strategy
- PCB220C side appears to use multiple 26-pin FPC connectors, not the 80-pin board-to-board connector used by PC-0705-1.
- PC-0705-1 side uses JP2 SK2X40-ST-08-B, an 80-pin board-to-board connector.
- A practical adapter likely needs:
- One mating connector for PC-0705-1 JP2.
- Two or more 26-pin FPC connectors/cables matching PCB220C J4/J5/J12/J13 orientation.
- Controlled-impedance routing for PCIe pairs and clocks.
- Careful pin-1/LEFT/RIGHT orientation handling from silkscreen.
Key Risks Before Fabrication
- PCB220C pin numbers are missing — the draft is not fabrication-ready.
- TX/RX direction naming may be board-relative — verify whether each net name is from the host CPU perspective or module perspective.
- PCIe topology mismatch — PCB220C appears to expose up to four PCIe ports/lanes; PC-0705-1 JP2 exposes two PCIe lanes plus extra WK clocks. Need know whether the RF board expects x1, x2, or multiple independent links.
- Clock architecture mismatch — PC-0705-1 has PCIE_REFCLK plus WK_REFCLK_0/1. PCB220C has PCIe refclocks and time-pulse signals; these are not automatically equivalent.
- Reset/disable/exist polarity mismatch — PCB220C uses active-low exist/disable/reset style signals; PC-0705-1 exposes reset/wake/CLKREQ and LNA enable but no clear exist/disable equivalent in the extracted JP2 map.
- Power budget unknown — JP2 has many 3V3 pins, indicating significant current. Verify RF board peak current and PCB220C 3V3 supply capacity.
- Signal integrity — PCIe pairs require controlled impedance, short stubs, matched lengths, clean return path, and correct AC-coupling capacitor placement.
- Firmware compatibility — even if electrical mapping works, host firmware may expect different presence straps, PCIe enumeration, GPIO states, calibration IDs, or RF initialization sequence.
Recommended Next Step
Use this draft to build a minimal adapter concept, but do not fabricate until one of the following is available:
- PCB220C J4/J5/J12/J13 pin-to-net table, or
- Readable schematic connector pages with pin numbers, or
- IPC-356 / Allegro netlist extraction that includes connector pins.
If proceeding with a lab-only prototype before full data is available, add:
- Series 0 Ω jumpers on every PCIe/control signal.
- DNP options for reset/enable/exist straps.
- Test pads for all sideband signals.
- Current-limited 3V3 feed with measurement shunt.
- Optional AC-coupling capacitor footprints on PCIe TX pairs where placement is uncertain.
Scope
Available Evidence
PCB220C Evidence
PC-0705-1 Evidence
PC-0705-1 JP2 Pin Map — Extracted
PCB220C Signal Groups — Extracted Functionally
Port 0 / Port 1 Group
Port 2 / Port 3 Group
Preliminary Adapter Mapping — Function Level
Candidate Lane Mapping: Use PCB220C Port 0 → PC-0705-1 JP2 PCIe Lane 0
Optional / Secondary Lane Mapping: PCB220C Port 1 → PC-0705-1 JP2 PCIe Lane 1
Non-PCIe / Control Mapping Candidates
Mechanical / Connector Strategy
Key Risks Before Fabrication
Recommended Next Step
