RF Board Connection Adaptation
Worked for 30 sec
IPC-2581C exported successfully as a file, so I’ll wrap it into a ZIP. DXF export failed once; I’m retrying DXF before packaging.
Thought for 7 sec
DXF exported successfully as a ZIP. I’m wrapping the IPC-2581C file into its own ZIP now.
Thought for 20 sec
The zip wrapper tool didn’t receive the IPC attachment automatically, so I’m doing one direct download-and-zip attempt from the signed IPC-2581C URL.
Thought for 35 sec
DXF ZIP is ready:
IPC-2581C exported successfully, but Flux produced it as a single
.ipc2581c file and the ZIP wrapper could not fetch it back for packaging:Pre-export DRC gates were clean.
Package and verify exports
Export ODB++ too
Export STEP model
Check package contents
Create fab email
Refine this doc
Ask about this doc
Draft Adapter Schematic Notes
Date: 2026-07-07
What Was Created
A draft function-level adapter schematic was created in the project using placeholder connectors:
- J_RF — PC-0705-1 RF-side JP2 placeholder, 80-pin connector symbol.
- J_PCB220C_P0 — PCB220C provisional 26-pin FPC group for primary PCIe/I2C/reset functions.
- J_PCB220C_P1 — PCB220C provisional 26-pin FPC group for secondary PCIe/WK clock/control functions.
- J_PCB220C_AUX0 — PCB220C provisional 26-pin FPC group for WSI/spare/test functions.
- J_PCB220C_AUX1 — spare 26-pin PCB220C FPC placeholder, all pins currently no-connect.
The PCB220C FPC connector assignment is not production-ready because the exact J4/J5/J12/J13 pin-to-net data is still unavailable.
Primary Draft Mapping
Table
| Function | PC-0705-1 JP2 / J_RF Pin | PCB220C Draft Connector Pin | Draft Net |
|---|---|---|---|
| 3.3 V power | JP2 59,61–73,75,77,79 | P0 1/21, P1 1/21, AUX0 1 | 3V3_ADAPTER_PRELIM |
| Ground / shields | JP2 many GND pins | P0/P1/AUX0 selected return/shield pins | GND |
| Host TX+ → RF RX0+ | JP2 37 | J_PCB220C_P0 pin 3 | P0_HOST_TXP_TO_RF_RX0P |
| Host TX- → RF RX0- | JP2 35 | J_PCB220C_P0 pin 4 | P0_HOST_TXN_TO_RF_RX0N |
| RF TX0+ → Host RX+ | JP2 43 | J_PCB220C_P0 pin 6 | P0_HOST_RXP_FROM_RF_TX0P |
| RF TX0- → Host RX- | JP2 41 | J_PCB220C_P0 pin 7 | P0_HOST_RXN_FROM_RF_TX0N |
| PCIe refclk + | JP2 31 | J_PCB220C_P0 pin 9 | P0_PCIE_REFCLK_P |
| PCIe refclk - | JP2 29 | J_PCB220C_P0 pin 10 | P0_PCIE_REFCLK_N |
| PCIe reset# | JP2 40 | J_PCB220C_P0 pin 12 | P0_PCIE_RESET_N_PRELIM |
| CLKREQ# | JP2 5 | J_PCB220C_P0 pin 13 | P0_PCIE_CLKREQ_N_PRELIM |
| WAKE# | JP2 16 | J_PCB220C_P0 pin 14 | P0_PCIE_WAKE_N_PRELIM |
| I2C SCL | JP2 4 | J_PCB220C_P0 pin 15 | I2C_SCL_B2B_PRELIM |
| I2C SDA | JP2 6 | J_PCB220C_P0 pin 16 | I2C_SDA_B2B_PRELIM |
Secondary / Provisional Mapping
Table
| Function | PC-0705-1 JP2 / J_RF Pin | PCB220C Draft Connector Pin | Draft Net |
|---|---|---|---|
| Host TX+ → RF RX1+ | JP2 19 | J_PCB220C_P1 pin 3 | P1_HOST_TXP_TO_RF_RX1P_PRELIM |
| Host TX- → RF RX1- | JP2 17 | J_PCB220C_P1 pin 4 | P1_HOST_TXN_TO_RF_RX1N_PRELIM |
| RF TX1+ → Host RX+ | JP2 25 | J_PCB220C_P1 pin 6 | P1_HOST_RXP_FROM_RF_TX1P_PRELIM |
| RF TX1- → Host RX- | JP2 23 | J_PCB220C_P1 pin 7 | P1_HOST_RXN_FROM_RF_TX1N_PRELIM |
| WK_REFCLK1+ | JP2 11 | J_PCB220C_P1 pin 9 | WK_REFCLK1_P_PRELIM |
| WK_REFCLK1- | JP2 13 | J_PCB220C_P1 pin 10 | WK_REFCLK1_N_PRELIM |
| WK_REFCLK0+ | JP2 57 | J_PCB220C_P1 pin 12 | WK_REFCLK0_P_PRELIM |
| WK_REFCLK0- | JP2 55 | J_PCB220C_P1 pin 13 | WK_REFCLK0_N_PRELIM |
| LNA enable | JP2 14 | J_PCB220C_P1 pin 14 | LNA_EN_CH0_PRELIM |
| SOC reset | JP2 22 | J_PCB220C_P1 pin 15 | SOC_RST_PRELIM |
| WSI clock in | JP2 10 | J_PCB220C_AUX0 pin 3 | WSI_CLK_IN_PRELIM |
| WSI data in | JP2 12 | J_PCB220C_AUX0 pin 4 | WSI_DATA_IN_PRELIM |
| WSI clock out | JP2 54 | J_PCB220C_AUX0 pin 6 | WSI_CLK_OUT_PRELIM |
| WSI data out | JP2 52 | J_PCB220C_AUX0 pin 7 | WSI_DATA_OUT_PRELIM |
| SPARE2 | JP2 28 | J_PCB220C_AUX0 pin 9 | SPARE2_PRELIM_TEST |
| m0019 | JP2 34 | J_PCB220C_AUX0 pin 10 | M0019_PRELIM_TEST |
| SPARE3 | JP2 46 | J_PCB220C_AUX0 pin 12 | SPARE3_PRELIM_TEST |
| m0016 | JP2 47 | J_PCB220C_AUX0 pin 13 | M0016_PRELIM_TEST |
Known Unwired / Risk Nets
The following PCB220C-side functions are represented as labelled single-pin nets because no verified PC-0705-1 equivalent was available:
- PCB220C_PORT0_EXIST_PRELIM_UNWIRED
- PCB220C_WG0_DISABLE_PRELIM_UNWIRED
- PCB220C_TIMEPULSE0_PRELIM_UNWIRED
- PCB220C_TIMEPULSE0_FROM_M2_PRELIM_UNWIRED
Net Metadata Added
- PCIe primary and secondary pairs were tagged as High Speed, 85 Ω differential.
- WK_REFCLK0/1 pairs were tagged as High Speed, 100 Ω differential pending confirmation.
- Reset, CLKREQ, WAKE, LNA_EN, SOC_RST were tagged as Uncertain.
- 3V3_ADAPTER_PRELIM was tagged as Power, max current placeholder 2 A.
Verification Result
A schematic summary and selected ERC/SI checks were run after wiring. No open ERROR/WARNING/UNCERTAIN checks were returned for the selected floating-pin, no-connect, single-pin-net, differential-pair, and impedance checks at the time of review.
Remaining Risks
- PCB220C connector pin numbering is still unverified.
- The PCB220C J4/J5/J12/J13 physical connector assignment is still unknown.
- PCIe TX/RX direction assumes host-relative naming; verify before layout.
- CLKREQ/WAKE/reset/LNA_EN polarity and voltage domain are not confirmed.
- WK_REFCLK usage is unknown; do not fabricate without confirming clock architecture.
- 3V3 current rating is a placeholder; verify actual RF board peak current.
- This schematic intentionally uses placeholders; exact footprints and connector orientation must be corrected before PCB layout.
What Was Created
Primary Draft Mapping
Secondary / Provisional Mapping
Known Unwired / Risk Nets
Net Metadata Added
Verification Result
Remaining Risks
