RF Board Connection Adaptation

flux

I’ll export IPC-2581C and DXF now, then provide the downloadable ZIP/file links.

flux

Pre-export gates are clean. I’m exporting IPC-2581C and DXF now; if either export is not already zipped, I’ll wrap it into a ZIP.

flux

IPC-2581C exported successfully as a file, so I’ll wrap it into a ZIP. DXF export failed once; I’m retrying DXF before packaging.

flux

DXF exported successfully as a ZIP. I’m wrapping the IPC-2581C file into its own ZIP now.

flux

The zip wrapper tool didn’t receive the IPC attachment automatically, so I’m doing one direct download-and-zip attempt from the signed IPC-2581C URL.

flux

DXF ZIP is ready:
IPC-2581C exported successfully, but Flux produced it as a single .ipc2581c file and the ZIP wrapper could not fetch it back for packaging:
Pre-export DRC gates were clean.
Package and verify exports
Export ODB++ too
Export STEP model
Check package contents
Create fab email
Sign up to send

Files

Schematic

Layout

3D View

Draft Adapter Schematic Notes
Date: 2026-07-07
What Was Created
A draft function-level adapter schematic was created in the project using placeholder connectors:
  • J_RF — PC-0705-1 RF-side JP2 placeholder, 80-pin connector symbol.
  • J_PCB220C_P0 — PCB220C provisional 26-pin FPC group for primary PCIe/I2C/reset functions.
  • J_PCB220C_P1 — PCB220C provisional 26-pin FPC group for secondary PCIe/WK clock/control functions.
  • J_PCB220C_AUX0 — PCB220C provisional 26-pin FPC group for WSI/spare/test functions.
  • J_PCB220C_AUX1 — spare 26-pin PCB220C FPC placeholder, all pins currently no-connect.
The PCB220C FPC connector assignment is not production-ready because the exact J4/J5/J12/J13 pin-to-net data is still unavailable.
Primary Draft Mapping

Table

FunctionPC-0705-1 JP2 / J_RF PinPCB220C Draft Connector PinDraft Net
3.3 V powerJP2 59,61–73,75,77,79P0 1/21, P1 1/21, AUX0 13V3_ADAPTER_PRELIM
Ground / shieldsJP2 many GND pinsP0/P1/AUX0 selected return/shield pinsGND
Host TX+ → RF RX0+JP2 37J_PCB220C_P0 pin 3P0_HOST_TXP_TO_RF_RX0P
Host TX- → RF RX0-JP2 35J_PCB220C_P0 pin 4P0_HOST_TXN_TO_RF_RX0N
RF TX0+ → Host RX+JP2 43J_PCB220C_P0 pin 6P0_HOST_RXP_FROM_RF_TX0P
RF TX0- → Host RX-JP2 41J_PCB220C_P0 pin 7P0_HOST_RXN_FROM_RF_TX0N
PCIe refclk +JP2 31J_PCB220C_P0 pin 9P0_PCIE_REFCLK_P
PCIe refclk -JP2 29J_PCB220C_P0 pin 10P0_PCIE_REFCLK_N
PCIe reset#JP2 40J_PCB220C_P0 pin 12P0_PCIE_RESET_N_PRELIM
CLKREQ#JP2 5J_PCB220C_P0 pin 13P0_PCIE_CLKREQ_N_PRELIM
WAKE#JP2 16J_PCB220C_P0 pin 14P0_PCIE_WAKE_N_PRELIM
I2C SCLJP2 4J_PCB220C_P0 pin 15I2C_SCL_B2B_PRELIM
I2C SDAJP2 6J_PCB220C_P0 pin 16I2C_SDA_B2B_PRELIM
Secondary / Provisional Mapping

Table

FunctionPC-0705-1 JP2 / J_RF PinPCB220C Draft Connector PinDraft Net
Host TX+ → RF RX1+JP2 19J_PCB220C_P1 pin 3P1_HOST_TXP_TO_RF_RX1P_PRELIM
Host TX- → RF RX1-JP2 17J_PCB220C_P1 pin 4P1_HOST_TXN_TO_RF_RX1N_PRELIM
RF TX1+ → Host RX+JP2 25J_PCB220C_P1 pin 6P1_HOST_RXP_FROM_RF_TX1P_PRELIM
RF TX1- → Host RX-JP2 23J_PCB220C_P1 pin 7P1_HOST_RXN_FROM_RF_TX1N_PRELIM
WK_REFCLK1+JP2 11J_PCB220C_P1 pin 9WK_REFCLK1_P_PRELIM
WK_REFCLK1-JP2 13J_PCB220C_P1 pin 10WK_REFCLK1_N_PRELIM
WK_REFCLK0+JP2 57J_PCB220C_P1 pin 12WK_REFCLK0_P_PRELIM
WK_REFCLK0-JP2 55J_PCB220C_P1 pin 13WK_REFCLK0_N_PRELIM
LNA enableJP2 14J_PCB220C_P1 pin 14LNA_EN_CH0_PRELIM
SOC resetJP2 22J_PCB220C_P1 pin 15SOC_RST_PRELIM
WSI clock inJP2 10J_PCB220C_AUX0 pin 3WSI_CLK_IN_PRELIM
WSI data inJP2 12J_PCB220C_AUX0 pin 4WSI_DATA_IN_PRELIM
WSI clock outJP2 54J_PCB220C_AUX0 pin 6WSI_CLK_OUT_PRELIM
WSI data outJP2 52J_PCB220C_AUX0 pin 7WSI_DATA_OUT_PRELIM
SPARE2JP2 28J_PCB220C_AUX0 pin 9SPARE2_PRELIM_TEST
m0019JP2 34J_PCB220C_AUX0 pin 10M0019_PRELIM_TEST
SPARE3JP2 46J_PCB220C_AUX0 pin 12SPARE3_PRELIM_TEST
m0016JP2 47J_PCB220C_AUX0 pin 13M0016_PRELIM_TEST
Known Unwired / Risk Nets
The following PCB220C-side functions are represented as labelled single-pin nets because no verified PC-0705-1 equivalent was available:
  • PCB220C_PORT0_EXIST_PRELIM_UNWIRED
  • PCB220C_WG0_DISABLE_PRELIM_UNWIRED
  • PCB220C_TIMEPULSE0_PRELIM_UNWIRED
  • PCB220C_TIMEPULSE0_FROM_M2_PRELIM_UNWIRED
Net Metadata Added
  • PCIe primary and secondary pairs were tagged as High Speed, 85 Ω differential.
  • WK_REFCLK0/1 pairs were tagged as High Speed, 100 Ω differential pending confirmation.
  • Reset, CLKREQ, WAKE, LNA_EN, SOC_RST were tagged as Uncertain.
  • 3V3_ADAPTER_PRELIM was tagged as Power, max current placeholder 2 A.
Verification Result
A schematic summary and selected ERC/SI checks were run after wiring. No open ERROR/WARNING/UNCERTAIN checks were returned for the selected floating-pin, no-connect, single-pin-net, differential-pair, and impedance checks at the time of review.
Remaining Risks
  1. PCB220C connector pin numbering is still unverified.
  2. The PCB220C J4/J5/J12/J13 physical connector assignment is still unknown.
  3. PCIe TX/RX direction assumes host-relative naming; verify before layout.
  4. CLKREQ/WAKE/reset/LNA_EN polarity and voltage domain are not confirmed.
  5. WK_REFCLK usage is unknown; do not fabricate without confirming clock architecture.
  6. 3V3 current rating is a placeholder; verify actual RF board peak current.
  7. This schematic intentionally uses placeholders; exact footprints and connector orientation must be corrected before PCB layout.

  • What Was Created

  • Primary Draft Mapping

  • Secondary / Provisional Mapping

  • Known Unwired / Risk Nets

  • Net Metadata Added

  • Verification Result

  • Remaining Risks