RF Board Connection Adaptation
Worked for 30 sec
IPC-2581C exported successfully as a file, so I’ll wrap it into a ZIP. DXF export failed once; I’m retrying DXF before packaging.
Thought for 7 sec
DXF exported successfully as a ZIP. I’m wrapping the IPC-2581C file into its own ZIP now.
Thought for 20 sec
The zip wrapper tool didn’t receive the IPC attachment automatically, so I’m doing one direct download-and-zip attempt from the signed IPC-2581C URL.
Thought for 35 sec
DXF ZIP is ready:
IPC-2581C exported successfully, but Flux produced it as a single
.ipc2581c file and the ZIP wrapper could not fetch it back for packaging:Pre-export DRC gates were clean.
Package and verify exports
Export ODB++ too
Export STEP model
Check package contents
Create fab email
Refine this doc
Ask about this doc
PCB Layout Start Review
Date: 2026-07-16
Layout Setup
- Board outline set to 100 mm × 60 mm, rectangular with 1 mm corner radius and 1 mm universal keepout.
- Stackup set to Standard 6 Layer.
- Component area is approximately 1522 mm², giving about 25.4% fill on the 100 × 60 mm board.
- All components are placed on the top side.
Mechanical Placement
Key placements:
Table
| Designator | Placement intent | Final approximate position |
|---|---|---|
| J1 | PCB220C J13 FPC cable connector on left edge | Left edge, x ≈ -47 mm, y ≈ 0 mm, rotated 90° |
| J2 | SK2X40-ST-08-B RF-board B2B datum | Right-center, x ≈ 18 mm, y ≈ 0 mm |
| J3 | Micro-Fit 3.0 high-current 3V3 input | Right/bottom edge, x ≈ 43.9 mm, y ≈ -18.2 mm |
| C_AC_* | DNP PCIe AC-coupling options | Bottom corridor below J2, spaced for routing |
| Y1 / R_Y1 | 48 MHz XO and series resistor | Near lower side of J2 / 48 MHz route |
| C_BULK1/2/3 | 3V3 local bulk | Near J2 power cluster and J3 input |
| J4 / J5 | DNP WSI/I2C debug headers | Top-left/top edge area |
Checks Run
Targeted checks were run for:
- Components outside board
- Component body overlap
- Missing footprints
- Overlapping copper
- Stackup validation
- Pad access clearance
- Signal-integrity impedance
- Signal-integrity differential-pair checks
- Auto-route feasibility pre-check
Results
- DRC/impedance selected checks: no open ERROR/WARNING/UNCERTAIN findings.
- Auto-route feasibility: Board valid; no routing feasibility issues detected.
- Layout summary confirms 6 copper layers.
Remaining Layout Risks
- J2 mechanical validation remains mandatory — verify SK2X40-ST-08-B mating height, footprint, and RF-board standoff alignment against original CAD/mechanical drawings.
- Placement is a starting point, not final routed layout — routing has not yet been performed.
- PCIe AC-coupling caps are DNP options — final placement/population still depends on confirming whether PC-0706-1 already has AC-coupling caps.
- 6-layer stackup is template-based — before fabrication, confirm the fab house impedance calculator for 85 Ω PCIe differential and 100 Ω REFCLK differential targets.
Layout Setup
Mechanical Placement
Checks Run
Results
Remaining Layout Risks
