RF Board Connection Adaptation


flux

I’ll export IPC-2581C and DXF now, then provide the downloadable ZIP/file links.

flux

Pre-export gates are clean. I’m exporting IPC-2581C and DXF now; if either export is not already zipped, I’ll wrap it into a ZIP.

flux

IPC-2581C exported successfully as a file, so I’ll wrap it into a ZIP. DXF export failed once; I’m retrying DXF before packaging.

flux

DXF exported successfully as a ZIP. I’m wrapping the IPC-2581C file into its own ZIP now.

flux

The zip wrapper tool didn’t receive the IPC attachment automatically, so I’m doing one direct download-and-zip attempt from the signed IPC-2581C URL.

flux

DXF ZIP is ready:
IPC-2581C exported successfully, but Flux produced it as a single .ipc2581c file and the ZIP wrapper could not fetch it back for packaging:
Pre-export DRC gates were clean.
Package and verify exports
Export ODB++ too
Export STEP model
Check package contents
Create fab email

J2 BRD Footprint Mismatch Review
Date: 2026-07-16
Scope
Compared adapter-board J2 against the uploaded Allegro board file:
  • Uploaded source: PC-0705-1_END.brd
  • Connector in source BRD: JP2 / SK2X40-ST-08-B
  • Adapter connector: J2 / SK2X40-ST-08-B
This review supersedes the earlier comparison against the Flux sk2x40-st-08-b reference project. That reference project uses the same Flux part UID as the adapter, so it does not independently validate the real Allegro footprint.
Finding
Mechanical mismatch found.
The adapter J2 footprint is not geometrically equivalent to the JP2 footprint implied by the original PC-0705-1_END.brd data.
Evidence
Original BRD / PC-0705-1 Evidence
The uploaded BRD identifies JP2 as:
  • CONN-2X40_SK2X40-ST-08-B_BOARD
  • MPN/name: SK2X40-ST-08-B
  • Padstack reference: SMD19X79
From the earlier IPC coordinate extraction for PC-0705-1 JP2:
  • Adjacent pin pitch along the connector length is about 0.8 mm.
  • The two connector rows are separated by about 4.4 mm.
  • 40 positions per row give a pin-field length of about 31.2 mm.
  • Padstack SMD19X79 corresponds approximately to 0.48 mm × 2.0 mm SMD pads.
So the real JP2 footprint should be approximately:
  • Length: ~31.2 mm pin span, package length around 34 mm.
  • Row separation: ~4.4 mm.
  • Pad size: ~0.48 × 2.0 mm.
  • Pad rows: two long rows running along the connector length.
Adapter / Flux J2 Evidence
The adapter J2 footprint currently has:
  • Package rule: PCIE-SMD
  • Package size rule: 34 mm × 6 mm
  • Pin pitch rule: 0.8 mm
  • Pad size: 0.5 mm × 2.0 mm
  • Pad positions observed in the adapter footprint:
    • Rows at x = ±16.25 mm
    • Pin sequence spans approximately y = -15.6 mm to +15.6 mm
This means the adapter footprint places the two rows about 32.5 mm apart, with pins progressing along the Y axis. That is not the physical geometry of the PC-0705-1 JP2 footprint.
Mismatch Summary

Table


ItemPC-0705-1 JP2 expectedAdapter J2 currentStatus
Pin count8080OK
Pad size~0.48 × 2.0 mm0.5 × 2.0 mmOK / close
Pitch along row0.8 mm0.8 mmOK
Row separation~4.4 mm~32.5 mmMismatch
Pin-field length~31.2 mm~31.2 mm, but along wrong axisMismatch
Footprint orientationLong direction along connector lengthPad rows transposed/rotated relative to expected geometryMismatch
Mechanical trust levelOriginal BRD sourceDerived Flux custom partAdapter needs correction
Root Cause
The Flux SK2X40-ST-08-B part appears to have the pad array transposed: the footprint uses the 31.2 mm pin-span dimension as the row-to-row X separation, instead of as the along-row length. This makes the physical pad field far wider than the real connector footprint.
Because the adapter J2 and the sk2x40-st-08-b reference project share the same Flux part UID, the earlier reference-project comparison passed but was not a valid mechanical check against the original Allegro BRD.
Fix or replace the SK2X40-ST-08-B footprint so it matches the original JP2 geometry:
  1. Keep 80 terminals and existing pin names/order.
  2. Use pad size approximately 0.48 mm × 2.0 mm from SMD19X79.
  3. Use 0.8 mm pitch along the long axis.
  4. Use ~4.4 mm row separation.
  5. Use 40 positions per row spanning approximately 31.2 mm.
  6. Preserve pin-1 orientation from the original BRD/IPC data.
  7. After correcting the part, replace/reload adapter J2 and re-run placement/DRC.
Risk
Do not fabricate the current adapter layout with the existing J2 footprint. The connector pads will not mate to the RF board as intended.
  • Scope

  • Finding

  • Evidence

  • Original BRD / PC-0705-1 Evidence

  • Adapter / Flux J2 Evidence

  • Mismatch Summary

  • Root Cause

  • Recommended Correction

  • Risk