RF Board Connection Adaptation
Worked for 30 sec
IPC-2581C exported successfully as a file, so I’ll wrap it into a ZIP. DXF export failed once; I’m retrying DXF before packaging.
Thought for 7 sec
DXF exported successfully as a ZIP. I’m wrapping the IPC-2581C file into its own ZIP now.
Thought for 20 sec
The zip wrapper tool didn’t receive the IPC attachment automatically, so I’m doing one direct download-and-zip attempt from the signed IPC-2581C URL.
Thought for 35 sec
DXF ZIP is ready:
IPC-2581C exported successfully, but Flux produced it as a single
.ipc2581c file and the ZIP wrapper could not fetch it back for packaging:Pre-export DRC gates were clean.
Package and verify exports
Export ODB++ too
Export STEP model
Check package contents
Create fab email
Refine this doc
Ask about this doc
Board Bring-Up Plan — RF Board Adapter Draft
Scope
Prototype bring-up checklist for the RF adapter interposer connecting PCB220C J13/J1-side signals to the T260-FR2 / PC-0705-1 RF sub-board via J2.
This board has no MCU and no onboard regulator. Bring-up focuses on power integrity, connector continuity, 48 MHz reference clock, reset/strap states, PCIe/refclock continuity, and RF sub-board mating.
Prerequisites
- Current final manufacturing package exported 2026-07-19.
- Equipment: microscope, DMM, current-limited 3.3 V bench supply, oscilloscope >= 200 MHz for clocks/sideband checks, high-speed probing as available, PCIe-capable host/main board, RF sub-board, ESD tools.
- Do not install the RF sub-board until power shorts and connector orientation are verified.
- Treat as prototype-risk until fabricator confirms controlled impedance and J2 mechanical fit.
1. Visual and Mechanical Inspection
Table
| Item | Inspect | Pass Criteria |
|---|---|---|
| Board outline | 100 mm x 60 mm, rounded rectangle | Matches mechanical expectation |
| J2 | SK2X40-ST-08-B footprint, edge setback, orientation, solder joints | Pad field and orientation match PC-0705-1 source BRD; RF sub-board can mate without obstruction |
| J1 | FH34SRJ-26S-0.5SH(50) FPC connector | Pin-1/orientation confirmed against PCB220C J13 cable direction |
| J3 | Molex 430450400 4-pin power input | Correct connector orientation and solder quality |
| Y1 | 48 MHz oscillator | Orientation and solder joints correct |
| AC caps | C_AC_TX0_P/N, C_AC_TX1_P/N, C_AC_RX0_P/N, C_AC_RX1_P/N | Population state matches intended PCIe AC-coupling plan |
| DNP headers | J4 WSI header, J5 I2C header | Populate only if needed for debug/options |
2. Power Rail Verification
Table
| Rail / Net | Source | Expected Voltage | Measure At | Initial Current Limit | Pass Criteria |
|---|---|---|---|---|---|
| GND | J3 pin 4 / board ground | 0 V | J3 GND, J2 GND pads, J1 GND pins | N/A | All grounds continuous; no unexpected resistance |
| 3V3_RF_POWER | J3 pin 2 to J2 3V3 pins and C_BULK1/C_BULK2/C_BULK3 | 3.3 V | J3 pin 2, C_BULK1 P1, J2 3V3 pads | 100 mA first power without RF sub-board | 3.135-3.465 V, no excessive current or heating |
| 3V3_FPC_LOGIC_ONLY | J3 pin 1 / PCB220C-side logic rail | 3.3 V | J3 pin 1 and related FPC-side rail nodes | 50-100 mA first power | 3.135-3.465 V, no excessive current or heating |
| Y1 supply | 3V3_RF_POWER through local routing | 3.3 V | Y1 VDD pin | Same as board supply | 3.135-3.465 V |
Power Procedure
- With board unpowered and RF sub-board disconnected, measure resistance from 3V3_RF_POWER to GND and 3V3_FPC_LOGIC_ONLY to GND. Stop if near-short is found.
- Apply 3.3 V to J3 with current limit set to 50-100 mA and no RF sub-board installed.
- Verify 3V3_RF_POWER and 3V3_FPC_LOGIC_ONLY are in range.
- Check C_BULK1/C_BULK2/C_BULK3 polarity/temperature and confirm no component heats.
- Increase current limit only after no-load power checks pass.
3. Critical Signal Verification
Table
| Signal / Net | Component(s) | Expected State | Test Method | Pass Criteria |
|---|---|---|---|---|
| 48MHZ_REF / Y1_48MHZ_OUT | Y1, R_Y1, J2 REFCLK_48M_B2B_R | 48 MHz CMOS clock when enabled | Scope at Y1 OUT and after R_Y1 | Frequency near 48 MHz; clean 3.3 V CMOS swing appropriate for load |
| SOC_RST_R_RC | R_SOC_PU, C_SOC_RST, J2 SOC_RST_R | Pull-up with RC delay | Scope at C_SOC_RST/J2 SOC_RST_R during power-up | Monotonic release after 3.3 V rises; no stuck-low |
| PCI_WAKE_N_R_PULLUP | R_WAKE, J2 PCI_WAKE_N_R | Pulled high to 3.3 V by default | DMM/scope | High when not actively driven low |
| PCIE_CLKREQ_N_STRAPPED_LOW | R_CLKREQ, J2 PCIE_CLKREQ_N | Default low strap | DMM | Low level before host interaction |
| WLAN_DISABLE_STRAPPED_HIGH | R_WLAN_DIS, J2 PCIE_W_DISABLE_R | Default high strap | DMM | High level unless intentionally overridden |
| LNA_EN_CH0/2/3_STRAPPED_HIGH | R_LNA0/R_LNA2/R_LNA3 to J2 | Default high | DMM | High level at J2 pins |
| I2C_SCL_B2B_OPTION / I2C_SDA_B2B_OPTION | R_I2C_SCL/R_I2C_SDA, J5, J2 | 3.3 V pull-ups if populated | DMM/scope | Idle high; no bus contention |
4. Connector and Interface Tests
Table
| Connector | Purpose | Pins / Nets to Verify | Test Method |
|---|---|---|---|
| J1 FH34SRJ-26S | PCB220C/J13 FPC interface | PCIe lanes, refclk, PERST, 3V3/GND pins | Continuity from J1 to AC caps/J2; verify pin-1 orientation |
| J2 SK2X40-ST-08-B | RF sub-board connector | PCIe x2, refclk, reset, wake, CLKREQ, 48 MHz, 3V3, GND, WSI/I2C options | Continuity and mating fit check before power with RF sub-board |
| J3 Molex 430450400 | External 3.3 V power input | 3V3_RF_POWER, 3V3_FPC_LOGIC_ONLY, GND | Polarity, voltage, continuity, current-limit test |
| J4 TSW-104-07-G-S | DNP WSI/debug header | WSI_CLK_IN_DNP_HEADER, WSI_DATA_IN_DNP_HEADER, WSI_DATA_OUT_DNP_HEADER, WSI_CLK_OUT_DNP_HEADER | Populate only for debug; verify no accidental shorts |
| J5 TSW-104-07-G-S | I2C option/debug header | I2C_SCL_B2B_OPTION, I2C_SDA_B2B_OPTION | Optional bus access; verify idle high if used |
5. High-Speed / PCIe Validation
Table
| Interface | Nets | Expected Result | Pass Criteria |
|---|---|---|---|
| PCIe TX0/RX0 | PCIE0_L0_TXP/N_TO_JP2_TX0_P/N, PCIE0_L0_RXP/N_TO_JP2_RX0_P/N | Lane continuity through AC caps and J2 | Link trains or expected host diagnostic state |
| PCIe TX1/RX1 | PCIE0_L1_TXP/N_TO_JP2_TX1_P/N, PCIE0_L1_RXP/N_TO_JP2_RX1_P/N | Lane continuity through AC caps and J2 | Link trains or expected host diagnostic state |
| PCIe refclk | PCIE0_REFCLK_P/N | Differential refclk reaches J2 | Valid amplitude/frequency at receiver side if probeable |
| AC-coupling caps | Eight 220 nF PCIe caps | Correct population/orientation not polarity-sensitive | No missing cap on required lane; DNP state matches plan |
PCIe Procedure
- Confirm the fabricator stackup/trace geometry for controlled impedance before relying on eye/link margin results.
- Power adapter alone first, then mate RF sub-board, then connect the PCB220C/main-board side.
- Check refclk and PERST/reset timing before expecting PCIe enumeration.
- Attempt PCIe link training; record link width, speed, and error counters.
- If link fails, first verify: AC cap population, lane polarity/direction, PERST timing, CLKREQ state, WAKE state, and J2 seating.
6. Functional Validation
Table
| Test | Input | Expected Output | Pass Criteria |
|---|---|---|---|
| No-load power | 3.3 V on J3 only | Stable rails, 48 MHz present | Current within expected prototype baseline; no heating |
| RF sub-board attached | 3.3 V on J3 with RF sub-board mated | Rails remain stable | No brownout; no connector heating |
| 48 MHz reference | Y1 powered/enabled | 48 MHz at J2 REFCLK_48M_B2B_R | Frequency and level acceptable to RF board |
| PCIe enumeration | Host/main board connected | RF board detected by host | Link trains without persistent errors |
| Optional I2C | J5 populated/used | SDA/SCL idle high, optional transactions | No bus contention; expected ACKs if target present |
| Optional WSI | J4 populated/used | WSI signals observable | Signal toggling matches system expectation |
7. Expected Measurements Reference
Table
| Measurement | Location | Expected Value | Instrument |
|---|---|---|---|
| 3V3_RF_POWER | J3 pin 2 / C_BULK1 P1 / J2 3V3 pins | 3.3 V ±5% | DMM/scope |
| 3V3_FPC_LOGIC_ONLY | J3 pin 1 / FPC-side rail | 3.3 V ±5% | DMM/scope |
| 48MHZ_REF | Y1 OUT / R_Y1 / J2 REFCLK_48M_B2B_R | 48 MHz | Oscilloscope |
| SOC_RST_R_RC | C_SOC_RST / J2 SOC_RST_R | RC release to high | Scope |
| PCI_WAKE_N_R_PULLUP | R_WAKE P2 / J2 PCI_WAKE_N_R | High idle | DMM/scope |
| PCIE_CLKREQ_N_STRAPPED_LOW | R_CLKREQ / J2 PCIE_CLKREQ_N | Low idle | DMM/scope |
| WLAN_DISABLE_STRAPPED_HIGH | R_WLAN_DIS / J2 PCIE_W_DISABLE_R | High idle | DMM/scope |
Pass/Fail Summary
Table
| Test Section | Result | Notes |
|---|---|---|
| Visual/mechanical inspection | [ ] Pass / [ ] Fail | |
| J2 mating/orientation | [ ] Pass / [ ] Fail | |
| Pre-power resistance checks | [ ] Pass / [ ] Fail | |
| Power rails | [ ] Pass / [ ] Fail | |
| 48 MHz reference | [ ] Pass / [ ] Fail | |
| Reset/strap states | [ ] Pass / [ ] Fail | |
| Connector continuity | [ ] Pass / [ ] Fail | |
| PCIe/refclock validation | [ ] Pass / [ ] Fail | |
| Optional I2C/WSI headers | [ ] Pass / [ ] Fail |
Board Status: [ ] Ready for prototype system testing / [ ] Requires rework
Scope
Prerequisites
1. Visual and Mechanical Inspection
2. Power Rail Verification
Power Procedure
3. Critical Signal Verification
4. Connector and Interface Tests
5. High-Speed / PCIe Validation
PCIe Procedure
6. Functional Validation
7. Expected Measurements Reference
Pass/Fail Summary
