RF Board Connection Adaptation
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IPC-2581C exported successfully, but Flux produced it as a single
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Solution A Adapter Implementation Notes
Date: 2026-07-16
Source Applied
The pasted Solution A adaptation plan was applied to the draft schematic. This supersedes the earlier provisional multi-FPC draft. The active architecture is now:
PCB220C / A8K J13 26-pin FPC → ICC081A-ADP adapter → J2 80-pin B2B → PC-0706-1 / T260-FR2 RF board
Only PCB220C J13 / PCIe0 x2 is used as the host FPC interface. The prior placeholder connectors for additional PCB220C FPC ports were removed.
Main Schematic Blocks
Table
| Designator | Function | Notes |
|---|---|---|
| J1 | PCB220C J13-side FPC receptacle | FH34SRJ-26S-0.5SH(50), 26-pin FPC |
| J2 | RF-board 80-pin B2B placeholder | Placeholder for mate of SK2X40-ST-08-B / NT-0076-0 |
| J3 | Dedicated 3V3 power input | WIRE_3P placeholder; final connector should be high-current or solder pads |
| Y1 | 48 MHz XO | HSO321S 48 MHz 3.3 V; drives J2 pin 47 through R_Y1 |
| J4 | DNP WSI/debug header | 2x5 1.27 mm header; WSI signals only, not required by A8K path yet |
| J5 | DNP I2C_B2B header | 1x4 header with 2.2 kΩ pullups |
| R_CLKREQ | CLKREQ strap | 1 kΩ pull-down |
| R_WAKE | WAKE strap | 10 kΩ pull-up |
| R_WLAN_DIS | WLAN_DISABLE strap | 10 kΩ pull-up; jumper option to WG0_DISABLE_N not yet modeled |
| R_LNA0/R_LNA2/R_LNA3 | LNA enable straps | 10 kΩ pull-ups |
| C_BULK1/C_BULK2/C_BULK3 | 3V3 local bulk | 100 µF + 22 µF + 1 µF at J2 power cluster |
Verified J13 → J2 Mapping Implemented
Table
| PCB220C J13 net | J1 pin | RF B2B net / J2 pin | Implemented net |
|---|---|---|---|
| PCIE0_L0_TXP | 5 | PCIE_TX0_P / 43 | PCIE0_L0_TXP_TO_JP2_TX0_P |
| PCIE0_L0_TXN | 6 | PCIE_TX0_N / 41 | PCIE0_L0_TXN_TO_JP2_TX0_N |
| PCIE0_L0_RXP | 8 | PCIE_RX0_P / 37 | PCIE0_L0_RXP_TO_JP2_RX0_P |
| PCIE0_L0_RXN | 9 | PCIE_RX0_N / 35 | PCIE0_L0_RXN_TO_JP2_RX0_N |
| PCIE0_L1_TXP | 14 | PCIE_TX1_P / 25 | PCIE0_L1_TXP_TO_JP2_TX1_P |
| PCIE0_L1_TXN | 15 | PCIE_TX1_N / 23 | PCIE0_L1_TXN_TO_JP2_TX1_N |
| PCIE0_L1_RXP | 17 | PCIE_RX1_P / 19 | PCIE0_L1_RXP_TO_JP2_RX1_P |
| PCIE0_L1_RXN | 18 | PCIE_RX1_N / 17 | PCIE0_L1_RXN_TO_JP2_RX1_N |
| PCIE0_REFCLKP | 11 | PCIE_REFCLK_P / 31 | PCIE0_REFCLK_P |
| PCIE0_REFCLKN | 12 | PCIE_REFCLK_N / 29 | PCIE0_REFCLK_N |
| PCIE0_PERST_N | 21 | PCIE_RESETN_R / 40 | PCIE0_PERST_N_TO_JP2_RESETN_R |
| WG0_DISABLE_N | 22 | SOC_RST_R / 22 | WG0_DISABLE_TO_SOC_RST_OPTION |
| WG0_EXIST_N | 20 | No RF-side pin | Tied to GND |
| TIMEPULSE0 | 3 | Spare2/Spare3 option / 28 or 46 | TIMEPULSE0_JUMPER_INPUT plus labelled spare option nets |
| 3V3 logic | 1,2,25,26 | Adapter logic only | 3V3_FPC_LOGIC_ONLY |
| GND | 7,10,13,16,19,24 | Common RF GND pins | GND |
Adapter-Generated / Strap Mapping Implemented
Table
| Function | J2 pin(s) | Implementation |
|---|---|---|
| 3V3 RF power | 59,61,62,64,66,68–73,75,77,79 | From J3 via 3V3_RF_POWER, with 100 µF + 22 µF + 1 µF bulk caps |
| 48MHz_REF | 47 | Y1 XO output through R_Y1 = 33 Ω |
| WLAN_DISABLE | 34 | R_WLAN_DIS = 10 kΩ pull-up to 3V3_RF_POWER |
| PCIE_CLKREQ_N | 5 | R_CLKREQ = 1 kΩ pull-down to GND |
| PCI_WAKE_N_R | 16 | R_WAKE = 10 kΩ pull-up to 3V3_RF_POWER |
| LNA_EN_CH0/2/3 | 14 / 7 / 1 | 10 kΩ pull-ups to 3V3_RF_POWER |
| I2C_SCL/SDA_B2B | 4 / 6 | Routed to DNP J5 with 2.2 kΩ pull-ups |
| WSI_CLK/DATA IN/OUT | 10 / 12 / 52 / 54 | Routed to DNP J4 debug header |
| WK_REFCLK0/1 pairs | 57/55 and 11/13 | Labelled DNP_Y2 nets only; not connected to oscillator/buffer yet |
| Interrupt option | 9 and J1 pin 23 | Labelled separately; default NC, jumper not yet modeled |
Net Metadata
- PCIe data pairs: tagged High Speed, 85 Ω differential.
- PCIe REFCLK: tagged High Speed, 100 Ω differential.
- 48MHz_REF: tagged High Speed, 50 Ω single-ended.
- 3V3_RF_POWER: tagged Power, placeholder max current 5 A.
- 3V3_FPC_LOGIC_ONLY: tagged Power, limited-use logic rail; should not carry RF board bulk current.
Verification
A schematic summary and targeted checks were run after the update. Selected ERC/SI checks returned no open ERROR/WARNING/UNCERTAIN findings for floating pins, no-connects, single-pin nets, differential-pair, or impedance checks at the time of review.
Remaining Design Risks / Next Actions
- Replace the J2 placeholder with the exact SK2X40-ST-08-B mate footprint / NT-0076-0-derived part before layout.
- Replace J3 placeholder with a final high-current connector or solder-pad footprint rated for the measured RF-board current.
- Confirm Y1 oscillator jitter/ppm/output format against the QCA6438 48 MHz reference requirement.
- Add the actual RC/jumper network for SOC_RST_R if required; current schematic models the WG0_DISABLE_N → SOC_RST_R option as a direct labelled connection.
- Decide whether to implement physical solder jumpers for TIMEPULSE0→Spare2/Spare3 and interrupt→J13 pin 23.
- Determine whether WK_REFCLK0/1 need DNP oscillator/buffer footprints or only test pads.
- Add DNP AC-coupling capacitor footprints on PCIe TX pairs only after verifying whether PC-0706-1 already has the required caps.
- Layout must enforce short FFC, short adapter routes, solid GND reference, via stitching, and ≤0.1 mm intra-pair skew.
Source Applied
Main Schematic Blocks
Verified J13 → J2 Mapping Implemented
Adapter-Generated / Strap Mapping Implemented
Net Metadata
Verification
Remaining Design Risks / Next Actions
