RF Board Connection Adaptation

flux

I’ll export IPC-2581C and DXF now, then provide the downloadable ZIP/file links.

flux

Pre-export gates are clean. I’m exporting IPC-2581C and DXF now; if either export is not already zipped, I’ll wrap it into a ZIP.

flux

IPC-2581C exported successfully as a file, so I’ll wrap it into a ZIP. DXF export failed once; I’m retrying DXF before packaging.

flux

DXF exported successfully as a ZIP. I’m wrapping the IPC-2581C file into its own ZIP now.

flux

The zip wrapper tool didn’t receive the IPC attachment automatically, so I’m doing one direct download-and-zip attempt from the signed IPC-2581C URL.

flux

DXF ZIP is ready:
IPC-2581C exported successfully, but Flux produced it as a single .ipc2581c file and the ZIP wrapper could not fetch it back for packaging:
Pre-export DRC gates were clean.
Package and verify exports
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Files

Schematic

Layout

Preview

J2
J3
R_I2C_SDA
Resistance
2.2kΩ
R_LNA0
Resistance
10kΩ
R_SOC_GPIO_JMP
Resistance
0Ω
R_CLKREQ
Resistance
1kΩ
R_LNA2
Resistance
10kΩ
R_WAKE
Resistance
10kΩ
R_I2C_SCL
Resistance
2.2kΩ
R_Y1
Resistance
33Ω
R_SOC_PERST_JMP
Resistance
0Ω
R_WLAN_DIS
Resistance
10kΩ
R_SOC_PU
Resistance
10kΩ
R_LNA3
Resistance
10kΩ
C_BULK1
End of Life
Capacitance
100µF
C_AC_RX0_P
Capacitance
220nF
C_BULK2
Capacitance
22µF
C_AC_RX0_N
Capacitance
220nF
C_AC_TX1_P
Capacitance
220nF
C_AC_TX1_N
Capacitance
220nF
C_AC_RX1_P
Capacitance
220nF
C_AC_TX0_N
Capacitance
220nF
C_BULK3
Capacitance
1µF
C_AC_TX0_P
Capacitance
220nF
C_AC_RX1_N
Capacitance
220nF
C_SOC_RST
Capacitance
1µF
J1
Y1
J4
J5
Manufacturing Release Summary — RF Board Adapter Draft
Release Status
Prototype manufacturing package generated for RF Board Adapter Draft on 2026-07-19.
This is a prototype release, not a production signoff. The package is suitable for prototype fabrication after the fabricator confirms controlled impedance and the team verifies J2 mechanical mating with the RF sub-board.
Final Export Review

Table

Export ItemStatusNotes
Gerber + drill ZIPGeneratedGerber ZIP includes copper, mask, silkscreen, outline, inner layers, and drill files.
IPC-356 netlistGeneratedUse for fabrication electrical test / netlist comparison.
BOM CSVsGeneratedFlux, JLCPCB, PCBWay, and other vendor-specific BOM variants generated.
Pick-and-place CSVsGeneratedOpenPNP and JLCPCB variants generated.
Fabrication notesGeneratedIncludes impedance and J2 mechanical caveats.
Pre-Export Validation Review

Table

GateResultEvidence
AirwiresPassNo open errors/warnings returned at final review.
Overlapping copperPassNo open errors/warnings returned at final review.
Missing footprintsPassNo open errors/warnings returned at final review.
Invalid layersPassNo open errors/warnings returned at final review.
Components outside boardPassNo open errors/warnings returned at final review.
Stackup validationPassNo open errors/warnings returned at final review.
BOM/MPN checksPassNo open errors/warnings returned at final review.
Board outlinePass100 mm x 60 mm rounded-rectangle board outline present.
Layer countPass6 copper layers configured.
Layout / Assembly Snapshot

Table

ItemValue
Board size100 mm x 60 mm
Copper layers6
Routed layout618 route segments, 73 smart vias, 179 vias reported in layout summary
Layout components30 placed top-side components
Main connectorsJ1 FH34SRJ-26S-0.5SH(50), J2 SK2X40-ST-08-B, J3 Molex 430450400
Critical clockY1 HSO321S 48 MHz 3.3 V oscillator
PCIe AC couplingEight 220 nF DNP/population-controlled AC-coupling positions
BOM Snapshot

Table

Part / GroupQuantityNotes
Generic resistors11Includes I2C pull-ups, straps, jumpers, series clock resistor
Generic capacitors4 BOM-populatedBulk/RC caps; PCIe AC caps may be DNP/population-controlled per assembly plan
J1 FH34SRJ-26S-0.5SH(50)1PCB220C/J13 FPC-side connector
J2 SK2X40-ST-08-B1RF sub-board connector; manufacturer listed as legacy/unknown CAD source, confirm procurement
Y1 HSO321S 48 MHz13.3 V oscillator
J3 Molex 43045040014-pin power input
Required Fabrication / Assembly Notes
  1. Controlled impedance required
    • PCIe and reference-clock differential pairs must be checked against the fabricator's actual 6-layer stackup.
    • Confirm dielectric constants, copper weights, finished copper thickness, soldermask, target trace/space, and impedance coupons.
    • Do not treat the current impedance as production-signed-off without fab confirmation.
  2. J2 mechanical fit is critical
    • J2 footprint was corrected to match the PC-0705-1 source BRD geometry used by the mating RF sub-board.
    • Verify pad field, rotation, edge setback, mating height, connector overhang, and keepout before assembly.
    • Keep the J2-side RF sub-board mating corridor clear of tall components or hardware.
  3. Assembly options / DNPs
    • Confirm population state for PCIe AC-coupling capacitors before ordering assembly.
    • Confirm whether optional J4 WSI and J5 I2C headers should be populated.
    • Confirm strap resistor options for reset, CLKREQ, WLAN_DISABLE, LNA_EN, and WAKE states.
Release Risks / Open Signoffs

Table

RiskSeverityOwner / Action
Controlled impedance not independently verified by fabHigh for PCIe marginFabricator + electrical owner must confirm stackup and trace geometry
J2 mechanical/mating fitHigh for assembly successMechanical/electrical owner must compare against RF sub-board CAD and connector drawing
J2 sourcing/manufacturer metadataMediumProcurement must confirm exact SK2X40-ST-08-B source and assembly handling
PCIe AC-coupling populationMediumElectrical owner must confirm whether onboard caps are populated or DNP based on RF board cap location
Pick-and-place rotationsMediumAssembly house must verify rotations, especially J1/J2/J3/Y1
Send the fabricator/assembler:
  • Gerber/drill ZIP
  • IPC-356 netlist
  • BOM CSV matching the selected assembler format
  • Pick-and-place CSV matching the selected assembler format
  • Fabrication notes file
  • This release summary
Pre-Order Checklist
  • Open Gerbers in independent viewer and verify outline/layers/drills.
  • Confirm J2 orientation and RF sub-board clearance visually against source BRD/CAD.
  • Confirm controlled-impedance stackup with fabricator.
  • Confirm AC-coupling cap and optional header DNP/population states.
  • Verify BOM quantities and procurement availability.
  • Ask assembler to check pick-and-place rotations before build.
  • Use the Board Bring-Up Plan for first-article testing.
Release Decision
Prototype fabrication: Approved after impedance and J2 mechanical caveats are acknowledged.
Production fabrication: Not approved until controlled impedance, J2 mechanical fit, and first-article bring-up results are signed off.

  • Release Status

  • Final Export Review

  • Pre-Export Validation Review

  • Layout / Assembly Snapshot

  • BOM Snapshot

  • Required Fabrication / Assembly Notes

  • Release Risks / Open Signoffs

  • Recommended Order Package

  • Pre-Order Checklist

  • Release Decision