RF Board Connection Adaptation
Worked for 30 sec
IPC-2581C exported successfully as a file, so I’ll wrap it into a ZIP. DXF export failed once; I’m retrying DXF before packaging.
Thought for 7 sec
DXF exported successfully as a ZIP. I’m wrapping the IPC-2581C file into its own ZIP now.
Thought for 20 sec
The zip wrapper tool didn’t receive the IPC attachment automatically, so I’m doing one direct download-and-zip attempt from the signed IPC-2581C URL.
Thought for 35 sec
DXF ZIP is ready:
IPC-2581C exported successfully, but Flux produced it as a single
.ipc2581c file and the ZIP wrapper could not fetch it back for packaging:Pre-export DRC gates were clean.
Package and verify exports
Export ODB++ too
Export STEP model
Check package contents
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Finalization Review Notes
Date: 2026-07-16
Changes Completed
J2 Finalized
- Replaced the temporary 80-pin header placeholder with SK2X40-ST-08-B.
- J2 now uses named terminals matching the Solution A / B2B pinout, including:
- PCIe x2 signals
- PCIE_REFCLK_P/N
- PCIE_RESETN_R
- SOC_RST_R
- WSI signals
- I2C_B2B
- LNA_EN_CH0/2/3
- 48MHz_REF
- 3V3/GND pin bank
- Important caveat: the part description still notes that the exact land pattern is based on extracted legacy CAD data and should be verified against the mechanical drawing before release.
J3 Finalized
- Replaced the temporary WIRE_3P placeholder with Molex Micro-Fit 3.0 430450400, 4-circuit high-current connector.
- Wired as:
- J3 pins 1/2 → 3V3_RF_POWER
- J3 pins 3/4 → GND
- 3V3_RF_POWER remains annotated as a 5 A design-intent rail.
SOC_RST RC / Jumpers Added
Added:
- R_SOC_PU = 10 kΩ pull-up from 3V3_RF_POWER to SOC_RST_R_RC.
- C_SOC_RST = 1 µF from SOC_RST_R_RC to GND.
- R_SOC_GPIO_JMP = 0 Ω jumper from WG0_DISABLE_N GPIO path to SOC_RST_R_RC.
- R_SOC_PERST_JMP = 0 Ω DNP jumper option from PCIE0_PERST_N to SOC_RST_R_RC.
J2 SOC_RST_R now connects to SOC_RST_R_RC, not directly to the host GPIO.
PCIe DNP AC-Coupling Footprints Added
Added 220 nF 0402 coupling-cap footprints for all PCIe x2 data pairs:
- C_AC_TX0_P / C_AC_TX0_N
- C_AC_RX0_P / C_AC_RX0_N
- C_AC_TX1_P / C_AC_TX1_N
- C_AC_RX1_P / C_AC_RX1_N
These are marked Exclude from BOM = true as DNP options. Populate only after confirming PC-0706-1 does not already include the required PCIe AC-coupling capacitors. The schematic now routes the PCIe nets through these footprints to preserve the option in layout.
BOM Metadata Updated
Populated generic passives were assigned packages and candidate MPNs:
- 10 kΩ 0402 straps: Yageo RC0402FR-0710KL
- 2.2 kΩ 0402 I2C pull-ups: Yageo RC0402FR-072K2L
- 1 kΩ 0402 CLKREQ pull-down: Yageo RC0402FR-071KL
- 33 Ω 0402 clock series resistor: Yageo RC0402FR-0733RL
- 0 Ω 0402 SOC GPIO jumper: Yageo RC0402JR-070RL
- 100 µF bulk: Murata GRM32ER60J107ME20L
- 22 µF bulk: Murata GRM21BR60J226ME39L
- 1 µF decoupling/timing: Murata GRM155R61C105KE15D
Review Results
Targeted ERC/BOM/SI review was run after the finalization pass:
- Floating pins: no open issues reported.
- No-connect / single-pin nets: no open issues reported.
- Missing footprints: no open issues reported.
- Manufacturer Part Number / BOM review: no open issues reported.
- Parts availability / basic part metadata checks: no open issues reported in the selected review set.
- Differential-pair / impedance checks: no open issues reported in the selected review set.
Remaining Engineering Risks
- J2 mechanical validation — SK2X40-ST-08-B footprint must still be verified against the original PC-0705-1/PC-0706-1 mechanical stackup and connector drawing.
- J3 current path — Micro-Fit 3.0 4-circuit is a reasonable high-current candidate; confirm cable gauge and current derating for measured RF-board peak current.
- PCIe cap assembly option — DNP caps are present in the schematic/layout path. Assembly decision must be made after checking where AC-coupling capacitors exist on PC-0706-1.
- SOC_RST timing — 10 kΩ / 1 µF gives roughly a 10 ms RC time constant; confirm QCA6438 reset timing requirements during bring-up.
- 48 MHz XO — HSO321S 48 MHz 3.3 V is implemented; confirm jitter/ppm compatibility with the RF board reference-clock requirement.
Changes Completed
J2 Finalized
J3 Finalized
SOC_RST RC / Jumpers Added
PCIe DNP AC-Coupling Footprints Added
BOM Metadata Updated
Review Results
Remaining Engineering Risks
