RF Board Connection Adaptation

IPC-2581C exported successfully as a file, so I’ll wrap it into a ZIP. DXF export failed once; I’m retrying DXF before packaging.
DXF exported successfully as a ZIP. I’m wrapping the IPC-2581C file into its own ZIP now.
The zip wrapper tool didn’t receive the IPC attachment automatically, so I’m doing one direct download-and-zip attempt from the signed IPC-2581C URL.
DXF ZIP is ready:
IPC-2581C exported successfully, but Flux produced it as a single .ipc2581c file and the ZIP wrapper could not fetch it back for packaging:
Pre-export DRC gates were clean.
Package and verify exports
Export ODB++ too
Export STEP model
Check package contents
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J2
J3
R_I2C_SDA
Resistance
2.2kΩ
R_LNA0
Resistance
10kΩ
R_SOC_GPIO_JMP
Resistance
J4
R_CLKREQ
Resistance
1kΩ
R_LNA2
Resistance
10kΩ
R_WAKE
Resistance
10kΩ
R_I2C_SCL
Resistance
2.2kΩ
R_Y1
Resistance
33Ω
R_SOC_PERST_JMP
Resistance
R_WLAN_DIS
Resistance
10kΩ
R_SOC_PU
Resistance
10kΩ
R_LNA3
Resistance
10kΩ
J1
C_BULK1
End of Life
Capacitance
100µF
C_AC_RX0_P
Capacitance
220nF
C_BULK2
Capacitance
22µF
C_AC_RX0_N
Capacitance
220nF
C_AC_TX1_P
Capacitance
220nF
C_AC_TX1_N
Capacitance
220nF
C_AC_RX1_P
Capacitance
220nF
C_AC_TX0_N
Capacitance
220nF
C_BULK3
Capacitance
1µF
C_AC_TX0_P
Capacitance
220nF
C_AC_RX1_N
Capacitance
220nF
C_SOC_RST
Capacitance
1µF
Y1
J5

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Final DRC / SI Cleanup Status
Date: 2026-07-19
Actions performed
  • Removed the bad overlap-producing J2 upper escape route and its dangling remnants.
  • Reran autoroute cleanup passes after removing the bad route fragments.
  • Repaired temporary 3V3/WSI dangling segments caused by cleanup attempts and restored routing to the current post-autoroute baseline.
  • Ran a targeted full DRC/SI review set covering airwires, overlaps, dangling traces, invalid layers, footprint/body/board checks, pad access, stackup validation, and selected impedance/differential-pair/SI checks.
  • Visually reviewed the PCIe/refclock route corridor between J1, AC-coupling caps, and J2.
Current review result
The latest review reports no open overlap, dangling-trace, protected-intrusion, invalid-layer, stackup, component-body, component-outside-board, pad-access, or selected SI/impedance warnings/errors.
Open DRC items are limited to three J2/GND airwires:

Table


CheckEndpoints reported
401437a5GND stitch via via.stitch.36 to J2 GND_15
GND_65J2 GND_65 to J2 GND_67
GND_76J2 GND_76 to J2 GND_74
Notes / risk
  • These three remaining items are connector-ground stitching/local ground continuity items on the SK2X40 J2 footprint.
  • Direct pad-to-pad routing and autoroute could not resolve them cleanly.
  • Manual multi-segment jumpers can clear the airwire checks, but they caused overlapping-copper DRC at segment joints or nearby existing copper, so they were removed to avoid hidden fabrication/short risk.
  • J2 GND pads already have direct/all-layer connection rules on the stubborn pads, but the checker still reports the above airwires.
Do not fabricate until these three J2 GND DRC items are resolved or formally accepted as same-net false positives after manual CAD review. Preferred next repair path is to edit the J2 footprint/copper geometry directly with a single continuous same-net copper shape per jumper, or update the connector footprint/pad access so the ground pads connect cleanly without trace-segment overlap reports.
  • Actions performed

  • Current review result

  • Notes / risk

  • Recommended next action

RF Board Adapter Draft thumbnail
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Properties

Properties describe core aspects of the project.

Pricing & Availability

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Qty 1

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$1.59–$2.48

Digi-Key

$0.74

HQonline

$0.44

LCSC

$3.97–$5.28

Mouser

$4.52

TME

$0.98

Verical

$1.90–$80.73

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