Project Status and Action Items
Worked for 1 min 27 sec
Done. I deleted
CN1 and moved U_MCU/Pico to the top of the board; it is now centered at about (10 mm, 88 mm) with its top edge just inside the board outline.Open item: the Pico was clamped at the board edge, so if you want more clearance from the top edge I can drop it slightly lower.
I need a power switch and some output LEDs
Thought for 5 sec
I’ll add a low-current front-panel power/enable switch rather than a high-current 12 V path switch, plus output/status LEDs with current-limiting resistors, then verify the schematic changes.
Worked for 1 min 54 sec
Added the power switch and output LEDs.
SW_PWR is a low-current front-panel switch that pulls Pico 3V3_EN to GND to turn logic off, and I added green indicators for BUS_12V and VOUT_19V5 with 4.7kΩ and 8.2kΩ series resistors.Open items:
- These are placed near the top/front-panel area but not routed yet.
- If you intended a true high-current input disconnect instead of a Pico enable switch, that needs a different switch/contactor architecture.
Route controls and verify
Use high-current switch
Route switch and LEDs
Add LED labels
Run design review
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Schematic Support Network and ERC Status
Completed in this pass
LM5122 boost daughterboard support network
Added and wired first-pass LM5122 support parts:
R_RT = 36.5 kΩfromSYNCIN/RTto GND for approximately 250 kHz first-pass switching frequency, matching the datasheet example value.R_SLOPE = 100 kΩfromSLOPEto GND as a first-pass slope-compensation value from the datasheet example.C_SS = 100 nFfromSSto GND for soft-start. Final soft-start time must be recalculated against the actual output capacitance and inrush target.C_VCC = 1 µFfromVCCto GND/PGND for local LM5122 bias decoupling.R_OPT_PD = 0 ΩfromOPTto GND so OPT is not floating and the controller is in free-running/master-style default behavior.R_MODE_PD = 0 ΩfromMODEto GND for diode-emulation/pulse-skipping first-pass light-load efficiency mode.REStied directly to GND, which disables hiccup-mode restart timing per the datasheet first-pass choice.CSPconnected to the upstream side ofR_SHUNT_IN;CSNconnected to the downstreamDB_VINside, so LM5122 cycle-by-cycle current sense is across the input shunt.- LM5122 NC pins and
SYNCOUTmarked no-connect where appropriate.
Pico 2 / distribution-board logic power
Added
U_LOGIC_BUCK as a first-pass 12 V to 5 V logic buck placeholder and wired:BUS_12V → U_LOGIC_BUCK VINU_LOGIC_BUCK OUTPUT/FB → 5V_LOGIC5V_LOGIC → Pico 2 VSYS/VBUSU_LOGIC_BUCK ON_OFF → GNDfor always-on behavior
This clears the previous Pico power ERC error, but the buck implementation is not final: the exact regulator variant, inductor, diode/synchronous topology, input/output capacitance, feedback wiring, and thermal/EMI layout still need validation.
ERC result after this pass
ERC status: warnings only, no current ERC errors.
Remaining warning categories:
- Unused Pico 2 GPIO/control/debug pins are floating because the final GPIO map is not locked yet.
- TPS259827 upstream eFuse pins remain unfinished:
dVdt,LDSTRT,EN/UVLO,IMON,NRETRY,RETRY_DLY,PG,ITIMER, andILIMneed final datasheet-derived networks.
Important blockers before layout/order
- LM5122 values are first-pass only.
R_RT,R_SLOPE,C_SS, compensation parts, inductor ripple/current-limit margin, MOSFET losses, and shunt dissipation must be recalculated for 12 V input, 19.5 V output, and up to 10 A output. - Input shunt value appears suspect. Existing
R_SHUNT_INis tied into both INA181 telemetry and LM5122 current limit; its value/power rating must be verified because the LM5122 current-limit threshold is ~75 mV and boost input current can exceed 17 A at high load. - Logic buck is a placeholder. The selected
LM2596S-12RGlibrary part must be verified for the intended 5 V output and completed with required external components, or replaced with a cleaner modern buck such as LMR33630-class device. - TPS259827 upstream eFuse is incomplete. Its limit/timer/UVLO/dVdt/retry/power-good network must be sized for the Dell PSU input and 65 A-class upstream system behavior.
- Pico GPIO allocation is incomplete. Unused GPIOs can remain floating during architecture, but final schematic should either connect, label, or no-connect them intentionally.
- Connector placeholders remain. Bellwether HPSU, ED32BGFBK edge connector, and final 15 A barrel jack still need usable schematic-terminal/footprint mapping.
Recommended next fixes
- Finish TPS259827 support network and upstream input protection.
- Replace or complete
U_LOGIC_BUCKwith final 12 V to 5 V regulator implementation. - Recalculate LM5122 current limit, shunt value, slope compensation, compensation network, soft-start, and thermals.
- Assign Pico GPIOs for slot enable, status LED, temperature/current telemetry, fault/PGOOD, and future expansion.
- Repair/import final connectors and replace placeholders.
Completed in this pass
LM5122 boost daughterboard support network
Pico 2 / distribution-board logic power
ERC result after this pass
Important blockers before layout/order
Recommended next fixes
