Project Status and Action Items
Worked for 1 min 27 sec
Done. I deleted
CN1 and moved U_MCU/Pico to the top of the board; it is now centered at about (10 mm, 88 mm) with its top edge just inside the board outline.Open item: the Pico was clamped at the board edge, so if you want more clearance from the top edge I can drop it slightly lower.
I need a power switch and some output LEDs
Thought for 5 sec
I’ll add a low-current front-panel power/enable switch rather than a high-current 12 V path switch, plus output/status LEDs with current-limiting resistors, then verify the schematic changes.
Worked for 1 min 54 sec
Added the power switch and output LEDs.
SW_PWR is a low-current front-panel switch that pulls Pico 3V3_EN to GND to turn logic off, and I added green indicators for BUS_12V and VOUT_19V5 with 4.7kΩ and 8.2kΩ series resistors.Open items:
- These are placed near the top/front-panel area but not routed yet.
- If you intended a true high-current input disconnect instead of a Pico enable switch, that needs a different switch/contactor architecture.
Route controls and verify
Use high-current switch
Route switch and LEDs
Add LED labels
Run design review
Refine this doc
Ask about this doc
Edge Connector Pinout Rev A — Daughterboard Slot
Status
First-pass 32-pin pinout for the distribution-board to boost-daughterboard interface. The main schematic currently uses a placeholder 32-pin connector (
J_SLOT, X4622WVS-2x16I-C40D64-E60) because the exact ED32BGFBK import is footprint-only.Current Schematic Connector
- Placeholder:
J_SLOT - Part: X4622WVS-2x16I-C40D64-E60
- Purpose: schematic-only stand-in for the ED32BGFBK slot connector.
- Do not use this as the final PCB footprint.
Imported ED32BGFBK Status
- ED32BGFBK imported as Flux part: /kproc/ed32bgfbk
- Part UID:
63e570f9-6b31-4efa-8903-7a82ab48a548 - Manufacturer: WingTAT
- MPN: ED32BGFBK
- Verification result: import is currently footprint-only — 0 schematic terminals and 1 PCB layout node.
- Action required: add a schematic symbol with 32 electrical terminals and bind them to the imported footprint pads before using it in the final schematic/layout.
32-Pin Allocation
Table
| Pin | Net | Type | Notes |
|---|---|---|---|
| 1 | GND | Power Return | Interleaved high-current return |
| 2 | VIN_SLOT / SLOT1_12V | Power | +12V slot input |
| 3 | GND | Power Return | Interleaved high-current return |
| 4 | VIN_SLOT / SLOT1_12V | Power | +12V slot input |
| 5 | GND | Power Return | Interleaved high-current return |
| 6 | VIN_SLOT / SLOT1_12V | Power | +12V slot input |
| 7 | GND | Power Return | Interleaved high-current return |
| 8 | VIN_SLOT / SLOT1_12V | Power | +12V slot input |
| 9 | GND | Power Return | Interleaved high-current return |
| 10 | VIN_SLOT / SLOT1_12V | Power | +12V slot input |
| 11 | GND | Power Return | Interleaved high-current return |
| 12 | VIN_SLOT / SLOT1_12V | Power | +12V slot input |
| 13 | GND | Power Return | Interleaved high-current return |
| 14 | VIN_SLOT / SLOT1_12V | Power | +12V slot input |
| 15 | GND | Power Return | Interleaved high-current return |
| 16 | VIN_SLOT / SLOT1_12V | Power | +12V slot input |
| 17 | GND | Power Return | Interleaved high-current return |
| 18 | VIN_SLOT / SLOT1_12V | Power | +12V slot input |
| 19 | GND | Power Return | Interleaved high-current return |
| 20 | VIN_SLOT / SLOT1_12V | Power | +12V slot input |
| 21 | EN_SLOT / SLOT1_GATE | Digital Input to Daughterboard | Placeholder currently tied to enable/gate path; final topology TBD |
| 22 | MODE_SLOT / SLOT1_MODE | Digital Input to Daughterboard | Firmware-selectable LM5122 mode / efficiency control if supported |
| 23 | SYNC_SLOT / SLOT1_SYNC | Digital Input / Optional | Optional synchronizing clock; no-pop unless EMI requires it |
| 24 | FAULT_SLOT_N | Digital Output from Daughterboard | Open-drain fault recommended |
| 25 | PGOOD_SLOT | Digital Output from Daughterboard | Power-good / output-valid status |
| 26 | IIN_SENSE | Analog Output | Daughterboard input current monitor output |
| 27 | IOUT_SENSE | Analog Output | Daughterboard output current monitor output |
| 28 | TEMP_MOS | Analog Output | NTC divider near MOSFETs |
| 29 | TEMP_IND | Analog Output | NTC divider near inductor |
| 30 | VOUT_SENSE / VOUT_CONN | Analog Output | Placeholder direct output sense; final should be scaled/protected |
| 31 | MOD_PRESENT_N | Digital / Strap | Module present detect; short to GND or ID network on daughterboard |
| 32 | SLOT_ID_SPARE | Digital / Analog | Future ID strap, 1-Wire/I2C option, or spare |
Current Capacity Check
- VIN contacts: 10 × 3 A = 30 A theoretical.
- GND contacts: 10 × 3 A = 30 A theoretical.
- Expected full-load slot input: ~16.7 A at 12V for 180W output at 90% efficiency.
- Contact loading at 16.7 A: ~1.67 A/contact average before imbalance.
Layout Rules
- Interleave VIN and GND pins physically if the connector footprint permits it.
- Use a single GND net; do not create AGND in Rev A.
- Route analog telemetry away from switching nodes and SYNC.
- Add RC filtering and ADC input protection on analog telemetry lines.
- Treat SYNC as optional/no-pop; do not consume firmware complexity unless EMI testing requires it.
- Use MOD_PRESENT_N before enabling slot power.
Required Symbol Repair for ED32BGFBK
Create 32 schematic terminals using the table above. Recommended pin types:
- VIN_SLOT pins: Power In / Passive power contacts.
- GND pins: Ground.
- EN, MODE, SYNC: Input.
- FAULT_N, PGOOD, IIN_SENSE, IOUT_SENSE, TEMP_MOS, TEMP_IND, VOUT_SENSE: Output from daughterboard perspective.
- MOD_PRESENT_N, SLOT_ID_SPARE: Passive or bidirectional depending implementation.
Open Items
- Confirm exact ED32BGFBK physical pin numbering and side/orientation from the footprint/source library.
- Confirm whether pins are single-row numbering, dual-row A/B numbering, or card-edge side numbering.
- Decide whether SLOT_ID_SPARE becomes an analog ID resistor, 1-Wire EEPROM, I2C sideband, or remains spare.
Status
Current Schematic Connector
Imported ED32BGFBK Status
32-Pin Allocation
Current Capacity Check
Layout Rules
Required Symbol Repair for ED32BGFBK
Open Items
