Project Status and Action Items

K

kproc

Good job rotating the connectors. Delete CN1. I also want to move the Pico to the top of the board

flux

I’ll remove the extra CN1 connector and move the Pico module up toward the top edge of the PCB, then verify the placement.

flux

Done. I deleted CN1 and moved U_MCU/Pico to the top of the board; it is now centered at about (10 mm, 88 mm) with its top edge just inside the board outline.
Open item: the Pico was clamped at the board edge, so if you want more clearance from the top edge I can drop it slightly lower.
K

kproc

I need a power switch and some output LEDs

flux

I’ll add a low-current front-panel power/enable switch rather than a high-current 12 V path switch, plus output/status LEDs with current-limiting resistors, then verify the schematic changes.

flux

Added the power switch and output LEDs. SW_PWR is a low-current front-panel switch that pulls Pico 3V3_EN to GND to turn logic off, and I added green indicators for BUS_12V and VOUT_19V5 with 4.7kΩ and 8.2kΩ series resistors.
Open items:
  • These are placed near the top/front-panel area but not routed yet.
  • If you intended a true high-current input disconnect instead of a Pico enable switch, that needs a different switch/contactor architecture.
Route controls and verify
Use high-current switch
Route switch and LEDs
Add LED labels
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LM5122 UVLO / Slot Enable Review
Datasheet findings
From the attached TI LM5122 datasheet:
  • UVLO ~1.2 V: startup sequence begins, assuming VCC is above its UV threshold.
  • Once UVLO exceeds 1.2 V, the LM5122 enables an internal ~10 µA UVLO hysteresis current source.
  • TI explicitly allows remote shutdown by pulling UVLO below the standby/shutdown threshold with an open-drain/open-collector device.
  • UVLO must not be left floating.
Rev A schematic decision
For the representative daughterboard slot, Pico 2 slot control now flows as:
Pico 2 GPIO0 → 74LVC1G126 buffer → J_SLOT pin 21 EN → LM5122 UVLO
The daughterboard includes R_EN_PD = 100 kΩ from UVLO/EN to GND, so the boost module defaults off if the slot enable signal is absent or high impedance.
Important caveat
This Rev A wiring uses UVLO primarily as a logic enable. It does not yet implement an input-voltage UVLO divider from the daughterboard 12 V rail. That is acceptable as a first-pass control schematic because the upstream PSU/eFuse handles gross input validity, but before layout/order we should decide whether to add a local VIN-derived UVLO divider plus remote shutdown transistor for a true hardware undervoltage threshold.
Slot power-path decision
The previous Q_SLOT_EN high-side NMOS scaffold was removed. A 3.3 V GPIO/buffer cannot correctly drive a high-side 20 A NMOS switch without a proper high-side gate driver/charge pump. Rev A representative slot power is now:
BUS_12V → FH_SLOT blade fuse → J_SLOT VIN pins → daughterboard input shunt/filter/LM5122 VIN
Slot enable is handled by LM5122 UVLO rather than by disconnecting slot 12 V power.
Verification status
Connectivity verified after cleanup:
  • SLOT1_EN: U_MCU GPIO0 → U_SLOT_BUF A/Y → J_SLOT pin 21 → U1 UVLO, with R_EN_PD to GND.
  • SLOT1_12V: BUS_12V → FH_SLOT → J_SLOT VIN pins → daughterboard input shunt/current-sense/filter.
  • Q_SLOT_EN removed from the schematic to avoid implying a complete high-side power switch.
Remaining expected ERC items:
  • Pico 2 VBUS/VSYS power input path still needs the final distribution-board logic supply design.
  • TPS259827 support pins are still scaffolds and need final datasheet sizing/wiring.
  • LM5122 support pins CSN, CSP, SS, SLOPE, RES, OPT, etc. still need final datasheet-calculated networks.
  • Many unused Pico GPIOs are floating because the final GPIO allocation is not locked yet.

  • Datasheet findings

  • Rev A schematic decision

  • Important caveat

  • Slot power-path decision

  • Verification status