Project Status and Action Items
Worked for 1 min 27 sec
Done. I deleted
CN1 and moved U_MCU/Pico to the top of the board; it is now centered at about (10 mm, 88 mm) with its top edge just inside the board outline.Open item: the Pico was clamped at the board edge, so if you want more clearance from the top edge I can drop it slightly lower.
I need a power switch and some output LEDs
Thought for 5 sec
I’ll add a low-current front-panel power/enable switch rather than a high-current 12 V path switch, plus output/status LEDs with current-limiting resistors, then verify the schematic changes.
Worked for 1 min 54 sec
Added the power switch and output LEDs.
SW_PWR is a low-current front-panel switch that pulls Pico 3V3_EN to GND to turn logic off, and I added green indicators for BUS_12V and VOUT_19V5 with 4.7kΩ and 8.2kΩ series resistors.Open items:
- These are placed near the top/front-panel area but not routed yet.
- If you intended a true high-current input disconnect instead of a Pico enable switch, that needs a different switch/contactor architecture.
Route controls and verify
Use high-current switch
Route switch and LEDs
Add LED labels
Run design review
Refine this doc
Ask about this doc
Input Stage MOSFET Bank and 3.3 V Rail Notes
Schematic update
The upstream LM5069 hot-swap pass element uses a six-device parallel bank:
Q_HS1–Q_HS6: BSC0702LS, 60 V N-channel MOSFET.- All drains connected to
HOTSWAP_SENSE_NODE. - All sources connected to
BUS_12V. - LM5069 gate drive now goes through individual gate resistors:
R_HS_G1–R_HS_G6 = 10 Ω- Common drive:
HOTSWAP_GATE - Individual gate nets:
HOTSWAP_GATE_Q1–HOTSWAP_GATE_Q6
3.3 V logic rail support added:
C_3V3_BULK = 10 µFfrom3V3to GND.C_3V3_100N = 100 nFfrom3V3to GND.- Pico
ADC_VREFtied to3V3as a first-pass default.
BSC0702LS datasheet facts
From the BSC0702LS datasheet:
VDS = 60 VRDS(on), max = 2.7 mΩatVGS = 10 V,ID = 50 AID = 100 AatTC = 25°CID = 84 AatTC = 100°CID ≈ 23 Aunder the datasheet’s normal PCB thermal assumption (RθJA = 50 K/W)RθJCtypical 0.9 K/W, max 1.5 K/W- SOA curves are provided, but must be checked against actual startup/fault pulse timing.
Conduction-loss estimate at 150 A
Assuming six MOSFETs share current equally:
- Total current:
150 A - Current per FET:
25 A - Cold max
RDS(on):2.7 mΩ
Per-FET conduction loss:
P_FET = I² × R = 25² × 0.0027 ≈ 1.69 WTotal MOSFET bank conduction loss:
P_TOTAL = 6 × 1.69 W ≈ 10.1 WHot
RDS(on) will be higher. If using an approximate 1.5× hot resistance multiplier:- Per FET:
~2.5 W - Total bank:
~15 W
This is plausible only with serious copper, thermal spreading, and airflow. It is not layout-validated yet.
Kelvin shunt selection
Selected real shunt family/part:
R_HS_SHUNT: Bourns CSS4J-4026R-L300F- Four-terminal Kelvin current-sense resistor
R = 0.3 mΩ ±1%Power rating = 10 W @ 70°C terminal temperature- Same CSS4J-4026 datasheet family as the Flux-library 0.5 mΩ part.
LM5069 thresholds with
0.3 mΩ:- Current-limit threshold:
55 mV / 0.3 mΩ ≈ 183 A nominal - Min-current-limit estimate:
48.5 mV / 0.3 mΩ ≈ 162 A - Circuit-breaker threshold:
105 mV / 0.3 mΩ ≈ 350 A nominal - Shunt dissipation at 150 A:
150² × 0.0003 ≈ 6.75 W
This gives a hardware ceiling above 150 A while keeping shunt dissipation under the 10 W rating, assuming the PCB layout keeps terminal temperature within the datasheet derating curve.
LM5069 first-pass values
UVLO
Current first-pass divider:
R_HS_UV_TOP = 32.4 kΩR_HS_UV_BOT = 10 kΩ
Approximate falling threshold:
VUV_FALL ≈ 2.5 × (32.4k + 10k) / 10k ≈ 10.6 VApproximate hysteresis from LM5069 UVLO hysteresis current:
VHYS ≈ 21 µA × 32.4 kΩ ≈ 0.68 VApproximate rising threshold:
VUV_RISE ≈ 11.3 VThis is intended to keep the 12 V bus off during severe droop while allowing normal server PSU startup.
Power limit
Current first-pass value:
R_HS_PWR = 7.68 kΩ
Using the LM5069 datasheet equation, with
RSNS = 0.3 mΩ and about 14 V worst-case VDS, this targets roughly 250 W total MOSFET-bank power limit.Approximate power per MOSFET during power limit if sharing evenly:
250 W / 6 ≈ 42 W/FETThis still requires SOA validation against the BSC0702LS SOA curve for the selected timer and bus capacitance.
Timer
Current first-pass value:
C_HS_TIMER = 470 nF
LM5069 fault timeout estimate:
tFAULT ≈ C × 4 V / 85 µA ≈ 470 nF × 4 / 85 µA ≈ 22 msThis is long enough for moderate bus capacitance startup but increases stress during start-into-short. It must be validated with actual downstream capacitance and FET SOA.
SOA concerns
The biggest risk is not steady-state conduction loss; it is linear-mode stress during hot-swap events:
- Charging downstream bulk capacitance: during inrush, the MOSFETs can sit in the linear region while
BUS_12Vrises. - Start into short: the MOSFET bank may see nearly full input voltage while current/power limiting is active.
- Hot short while running: LM5069 must pull the gate down quickly enough and the FETs must survive until protection trips.
- Current sharing during linear operation: paralleled MOSFETs do not necessarily share equally during transient/linear events.
- Gate stability: individual gate resistors are now added, but values should be validated on hardware.
Remaining input-stage blockers
- Verify Bourns CSS4J-4026R-L300F sourcing/assembly availability for the intended manufacturer path.
- Validate shunt terminal temperature at 150 A continuous.
- Validate six-FET SOA for startup, start-into-short, and hot-short cases using actual bus capacitance.
- Confirm
R_HS_PWR = 7.68 kΩandC_HS_TIMER = 470 nFwith SOA calculations and/or simulation. - Perform layout-level thermal/current-density analysis before ordering.
- Add final HPSU connector pinout and PMBus/PSU enable details.
3.3 V rail status
The Pico is powered from the existing
5V_LOGIC rail via VSYS/VBUS, and its 3V3 rail powers local logic such as buffers, INA181 supplies, pull-ups, and status circuitry. Basic decoupling has been added, but the 5V_LOGIC buck remains a placeholder and still needs a final regulator implementation.Schematic update
BSC0702LS datasheet facts
Conduction-loss estimate at 150 A
Kelvin shunt selection
LM5069 first-pass values
UVLO
Power limit
Timer
SOA concerns
Remaining input-stage blockers
3.3 V rail status
