Schematic Execution Plan — Rackmount 12V Distribution PSU
Current Direction
Proceed with Rev A as a single-PSU, non-Ethernet, 12-slot-target distribution board plus LM5122 boost daughterboard interface. Use one validated slot/daughterboard channel first, then replicate after review.
Decisions Locked This Pass
- Per-slot protection baseline: LM5069MMX-1/NOPB hot-swap controller with external N-channel MOSFET and current-sense resistor.
- Why not integrated eFuse: JLC/Flux integrated eFuse candidates found were too low-current for ~16–20A continuous slot input.
- Fault behavior: LM5069-1 latches off on fault; MCU can reset by cycling UVLO/enable. This is safer than blind auto-retry for high-current slots.
- Edge connector: first-pass 32-pin pinout created in
edge-connector-pinout-rev-a-daughterboard-slot.
- Bellwether connector: PDFs are documented, but not importable EDA files. A custom component/footprint must be manually created from the Bellwether drawings or imported later from EDA library files.
Phase 1 — Custom Connector and Mechanical Baseline
- Manually create Bellwether 70012-1111 custom component and footprint using the supplied package and 2D drawings.
- Verify connector orientation, mounting holes, keying, and keepouts against the Dell D750E-S1 mechanical envelope.
- Create a rough board/chassis placement sketch before committing to 12 slots.
Phase 2 — One Distribution Slot Block
- Use LM5069MMX-1/NOPB as the first hot-swap controller candidate.
- Select external pass MOSFET(s), sense resistor, UVLO/OVLO divider, PWR resistor, TIMER capacitor, and PGD pull-up from the LM5069 datasheet/design calculator.
- Add one edge connector using the Rev A 32-pin pinout.
- Use 10 VIN and 10 GND contacts, interleaved where the physical connector permits.
- Drop AGND; use single GND and Kelvin/sense routing.
- Add EN, MODE, SYNC optional, FAULT, PGOOD, IIN, IOUT, TEMP_MOS, TEMP_IND, VOUT_SENSE, MOD_PRESENT, and SLOT_ID/SPARE.
Phase 3 — One Daughterboard Boost/Telemetry Block
- Wire the LM5122 boost stage from the user’s JLCPCB BoM after validating power-stage calculations.
- Add two INA181 current monitors: input-side 12V current and output-side 19.5V current.
- Add MOSFET and inductor thermistors.
- Add output voltage sense and hardware UVLO local to the daughterboard.
- Expose EN/MODE/FAULT/PGOOD/telemetry over the edge connector.
Phase 4 — MCU and Rev A Control
- Add Pico 2 / RP2350 controller and 3.3V logic power.
- Add USB/debug access.
- Add system status LED.
- Add enough ADC/mux/interface circuitry for the chosen analog telemetry strategy.
- Implement slot enable/fault handling for one slot first.
Phase 5 — Replication and Review
- Review the one-slot schematic electrically and mechanically.
- Replicate to 8, 10, or 12 slots depending on preliminary layout feasibility.
- Run ERC and power/thermal sanity checks.
- Pause before PCB layout routing until the slot count and physical arrangement are confirmed.
Immediate Decisions Still Needed
- Exact external pass MOSFET arrangement for each LM5069 slot: single MOSFET vs parallel MOSFETs.
- Sense resistor value and package/power rating for ~20A limit.
- Final ED32BGFBK footprint/pin-numbering confirmation.
- Whether analog telemetry goes directly to the distribution MCU or through daughterboard-local ADC/digital telemetry.
- Whether barrel jacks mount directly on daughterboards or to the rear panel with wiring.