Aurora Hearing Device Design

Blocked: your account is currently out of ACUs, so I can’t mutate the board/layout further in this run.
Accomplished this session:
  • Started the 12 mm product-like redesign workflow.
  • Loaded the required layout/component procedures for the crescent board, compact part replacement, and placement constraints.
  • Confirmed the next execution plan: 12 mm max-width smooth crescent, 4-layer stackup, compact USB-C replacement, high-SPL mic replacement, removal/shrinking of bulky hook-side parts, and dense two-sided placement.
Remaining:
  • Apply the new 12 mm crescent board outline and 4-layer stackup.
  • Replace/flag oversized parts: current USB-C, ICS-40730 mics, large flash, tactile switch, and bulky connectors.
  • Re-place the hook PCB components into the slim crescent form factor.
  • Run layout fit/congestion checks and update the project documentation.
Estimate the ACUs needed to finish the 12 mm redesign.
Estimate: ~25–45 ACUs to finish a credible 12 mm hook redesign pass.
Breakdown:
  • Apply 12 mm crescent outline + 4-layer stackup: 2–5 ACUs
  • Research/replace compact USB-C + high-SPL mics + smaller flash/switch/connectors: 6–12 ACUs
  • Re-place dense two-sided hook layout: 8–15 ACUs
  • Fit/congestion/layout verification: 4–8 ACUs
  • Update project docs and next-step notes: 2–5 ACUs
If we also route the board afterward, budget another 40–90 ACUs, because fine-pitch nRF5340/CS47L63, RF, USB, and dense wearable placement will likely need multiple iterations.
Proceed after ACUs
Prioritize fit check
Research compact parts
Update migration plan
Review power impact
Y1
SPK1
U6
J1
ANT1
J2
U5
U4
SPK3
MIC2
End of Life
SPK2
U3
MIC1
End of Life
J1 VBUS - U6 VBUS
U1 P0.22 - U2 ASP2_DIN/GPIO6
U2 VREF1_FILT - C21 P1
U1 VDD_3 - U1 VDD_4
U2 AS[1_DOUT/GPIO1 - U3 DAI2
J1 CC2 - R4 P1
L4 P2 - ANT1 FEEDING_POINT
U1 DECN - C18 P1
U8 EN - C6 P1
U1 VDD_9 - U1 VDDH
U2 VREF1_FILT - C21 P1
U1 DCC - L2 P1
MIC2 OUTPUT+ - C26 P1
U1 P0.24 - U2 IRQ
L4 P2 - ANT1 FEEDING_POINT
U1 VDD_9 - U1 VDDH
U2 VREF2_FILT - C22 P1
U1 NRESET - TP3 P1
U5 OUTN - SPK3 TERMINAL_1
U1 VDD_9 - U1 VDDH
U1 VDD_9 - U1 VDDH
U1 VDD_9 - U1 VDDH
C25 P2 - U2 IN1LN_1
U6 VSYS - U10 VIN
U1 VDD_9 - U1 VDDH
U8 BP - C8 P1
U1 VDD_9 - U1 VDDH
MIC2 OUTPUT+ - C26 P1
C27 P2 - U2 IN2LN
L2 P2 - U1 DECR
J1 D- - U1 D-
U1 P0.25/AIN4 - U3 EN
U6 VSYS - U10 VIN
J1 CC1 - R3 P1
J1 D- - U1 D-
U3 OUTN - SPK1 COIL_A
U5 OUTP - SPK3 TERMINAL_2
U6 NTC - R9 P1
U7 DI_(IO0) - U1 P0.13/IO0
U1 P0.25/AIN4 - U3 EN
U9 OUT - C10 P1
MIC1 OUTPUT- - C25 P1
U6 DEC - C23 P1
U1 P1.03/TWI - U2 SPI1_MOSI/I2C1_SDA
C24 P2 - U2 IN1LP_1
U1 P0.23 - U2 RESET
U1 P1.02/TWI - U2 SPI1_MISO/I2C1_SCL
U1 P0.25/AIN4 - U3 EN
J1 D+ - U1 D+
J3 1 - D1 A
U1 P0.21 - U2 ASP2_FSYNC/GPIO8
U6 VSYS - U10 VIN
U1 VDD_9 - U1 VDDH
U1 ANT - L4 P1
U9 OUT - C10 P1
L3 P2 - U1 DECD
U8 BP - C8 P1
U3 OUTP - SPK1 COIL_B
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U1 P0.23 - U2 RESET
U1 VDD_3 - U1 VDD_4
U9 EN - C9 P1
U7 ~WP_(IO2) - U1 P0.15/IO2
U3 OUTP - SPK1 COIL_B
U10 FB - R1 P2
U1 VDD_3 - U1 VDD_4
U7 ~WP_(IO2) - U1 P0.15/IO2
MIC1 OUTPUT- - C25 P1
U1 XC1 - Y1 XTAL1
U1 DECN - C18 P1
U7 DO_(IO1) - U1 P0.14/IO1
U1 P0.25/AIN4 - U3 EN
U6 VSYS - U10 VIN
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U2 AS[1_DOUT/GPIO1 - U3 DAI2
U1 XC2 - Y1 XTAL2
U1 XC2 - Y1 XTAL2
U7 ~HOLD_OR_~RESET_(IO3) - U1 P0.16/IO3
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U1 SWDIO - TP1 P1
MIC2 OUTPUT- - C27 P1
L4 P2 - ANT1 FEEDING_POINT
U1 P0.25/AIN4 - U3 EN
U1 DECUSB - C20 P1
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U6 VSYS - U10 VIN
U10 SW - L1 1
U7 ~CS - U1 P0.18/CSN
J1 CC2 - R4 P1
J1 VBUS - U6 VBUS
U7 CLK - U1 P0.17/SCK
U1 DECRF - C15 P1
U6 VSYS - U10 VIN
U1 VDD_9 - U1 VDDH
U1 P0.24 - U2 IRQ
U6 VSYS - U10 VIN
U1 P0.11/TRACEDATA0/CSN - SW1 1
U1 VDD_9 - U1 VDDH
J1 D+ - U1 D+
U1 VDD_9 - U1 VDDH
U2 AS[1_DOUT/GPIO1 - U3 DAI2
U3 OUTN - SPK1 COIL_A
C24 P2 - U2 IN1LP_1
U1 DECA - C19 P1
U6 NTC - R9 P1
U1 XC2 - Y1 XTAL2
U6 VSYS - U10 VIN
U6 DEC - C23 P1
C26 P2 - U2 IN2LP
U1 VDD_9 - U1 VDDH
U1 P1.02/TWI - U2 SPI1_MISO/I2C1_SCL
J3 1 - D1 A
U1 XC1 - Y1 XTAL1
U9 EN - C9 P1
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U1 P1.03/TWI - U2 SPI1_MOSI/I2C1_SDA
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U1 DCCD - L3 P1
U1 VDD_1 - U1 VDD_2
U1 DCC - L2 P1
L3 P2 - U1 DECD
U5 OUTP - SPK3 TERMINAL_2
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U4 OUTN - SPK2 N
U4 OUTN - SPK2 N
U9 OUT - C10 P1
U1 P0.21 - U2 ASP2_FSYNC/GPIO8
D1 K - U6 VBAT
J1 VBUS - U6 VBUS
U1 P0.25/AIN4 - U3 EN
U1 DECRF - C15 P1
J1 CC1 - R3 P1
U4 OUTP - SPK2 P
U9 OUT - C10 P1
U6 VSYS - U10 VIN
U2 AS[1_DOUT/GPIO1 - U3 DAI2
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U1 DCCD - L3 P1
C27 P2 - U2 IN2LN
U2 VREF2_FILT - C22 P1
U1 P0.11/TRACEDATA0/CSN - SW1 1
J1 D- - U1 D-
U6 ICHG - R8 P1
U1 P1.03/TWI - U2 SPI1_MOSI/I2C1_SDA
MIC1 OUTPUT+ - C24 P1
U1 VDD_9 - U1 VDDH
U1 XC1 - Y1 XTAL1
U10 SW - L1 1
U1 SWDIO - TP1 P1
U5 OUTN - SPK3 TERMINAL_1
U1 ANT - L4 P1
L2 P2 - U1 DECR
MIC1 OUTPUT+ - C24 P1
C25 P2 - U2 IN1LN_1
U2 AS[1_DOUT/GPIO1 - U3 DAI2
U1 DECRF - C15 P1
U1 P0.20 - U2 ASP2_BCLK/GPIO7
U6 VSYS - U10 VIN
MIC2 OUTPUT- - C27 P1
U4 OUTP - SPK2 P
U1 DECA - C19 P1
U1 VDD_9 - U1 VDDH
J1 D+ - U1 D+
U10 FB - R1 P2
U7 DI_(IO0) - U1 P0.13/IO0
U8 OUT - C7 P1
U1 SWDCLK - TP2 P1
C26 P2 - U2 IN2LP
U1 VDD_3 - U1 VDD_4
D1 K - U6 VBAT
U1 P1.02/TWI - U2 SPI1_MISO/I2C1_SCL
U8 EN - C6 P1
U6 ICHG - R8 P1
U6 VSYS - U10 VIN
U1 P0.22 - U2 ASP2_DIN/GPIO6
U1 ANT - L4 P1
U1 VDD_3 - U1 VDD_4
U10 FB - R1 P2
L3 P2 - U1 DECD
U6 VSYS - U10 VIN
U6 VSYS - U10 VIN
U8 EN - C6 P1
U8 OUT - C7 P1
U1 NRESET - TP3 P1
U1 P0.20 - U2 ASP2_BCLK/GPIO7
U8 OUT - C7 P1
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U1 VDD_1 - U1 VDD_2
U7 DO_(IO1) - U1 P0.14/IO1
U7 ~HOLD_OR_~RESET_(IO3) - U1 P0.16/IO3
U1 DECUSB - C20 P1
U1 VDD_9 - U1 VDDH
U10 FB - R1 P2
U1 VDD_9 - U1 VDDH
U7 CLK - U1 P0.17/SCK
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U6 VSYS - U10 VIN
U1 VDD_3 - U1 VDD_4
U7 ~CS - U1 P0.18/CSN
U1 SWDCLK - TP2 P1
C7 P2 - C8 P2
U6 AVSS_EP - U6 PVSS
C15 P2 - C16 P2
GND
R8 P2 - U6 ISET
U1 VSS_4 - U1 VSS_5
C7 P2 - C8 P2
U10 GND - C2 P2
C15 P2 - C16 P2
U10 GND - C2 P2
R8 P2 - U6 ISET
R8 P2 - U6 ISET
C30 P2 - C31 P2
U6 AVSS_EP - U6 PVSS
U1 AVSS_3 - U2 GND_A
J1 GND - R3 P2
U2 GND_D - U2 GND_SUB
U10 GND - C2 P2
R8 P2 - U6 ISET
Y1 GND - C4 P2
U2 GND_D - U2 GND_SUB
C21 P2 - C22 P2
ANT1 GND_2 - U2 VDD_LDO
C15 P2 - C16 P2
R7 P2 - U3 GAIN_SLOT
U1 AVSS_1 - U1 AVSS_2
R8 P2 - U6 ISET
J1 GND - R3 P2
U1 VSS_12 - U1 VSS_13
C15 P2 - C16 P2
U1 AVSS_3 - U2 GND_A
GND
U6 AVSS_EP - U6 PVSS
U5 GND_2 - J2 GND
R8 P2 - U6 ISET
C28 P2 - C29 P2
U1 AVSS_3 - U2 GND_A
U1 VSS_4 - U1 VSS_5
Y1 GND - C4 P2
U1 VSS_12 - U1 VSS_13
C7 P2 - C8 P2
U2 GND_D - U2 GND_SUB
ANT1 GND_2 - U2 VDD_LDO
R8 P2 - U6 ISET
U6 AVSS_EP - U6 PVSS
GND
U2 GND_D - U2 GND_SUB
C30 P2 - C31 P2
U10 GND - C2 P2
Y1 GND - C4 P2
U6 AVSS_EP - U6 PVSS
C21 P2 - C22 P2
U6 AVSS_EP - U6 PVSS
R8 P2 - U6 ISET
C15 P2 - C16 P2
U2 GND_D - U2 GND_SUB
U1 AVSS_3 - U2 GND_A
U10 GND - C2 P2
C15 P2 - C16 P2
C28 P2 - C29 P2
C21 P2 - C22 P2
GND
U1 AVSS_3 - U2 GND_A
R7 P2 - U3 GAIN_SLOT
U6 AVSS_EP - U6 PVSS
R8 P2 - U6 ISET
U6 AVSS_EP - U6 PVSS
C28 P2 - C29 P2
J1 GND - R3 P2
U10 GND - C2 P2
U5 GND_2 - J2 GND
U2 GND_D - U2 GND_SUB
U1 AVSS_1 - U1 AVSS_2
U10 GND - C2 P2
C31
Capacitance
DNP F
C8
Capacitance
0.01uF
C26
Capacitance
2.2 µF
C24
Capacitance
2.2 µF
C20
Capacitance
100nF
C13
Capacitance
1uF
C3
Capacitance
6.8pF
C9
Capacitance
1uF
C5
Capacitance
12pF
C28
Capacitance
0.1 µF
C21
Capacitance
2.2uF
C27
Capacitance
2.2 µF
C30
Capacitance
DNP F
C22
Capacitance
10uF
C10
Capacitance
1uF
C18
Capacitance
100nF
C12
Capacitance
1uF
C23
Capacitance
10uF
C19
Capacitance
1uF
C14
Capacitance
10uF
C1
Capacitance
4.7uF
C2
Capacitance
10uF
C15
Capacitance
1uF
C25
Capacitance
2.2 µF
C29
Capacitance
0.1 µF
C6
Capacitance
0.1uF
C4
Capacitance
12pF
C16
Capacitance
2.2nF
C7
Capacitance
2.2uF
C17
Capacitance
1uF
C11
Capacitance
1uF
U1
R9
Resistance
10kΩ
SW1
R4
Resistance
5.1kΩ
U2
R6
Resistance
4.7kΩ
R2
Resistance
100kΩ
R3
Resistance
5.1kΩ
R7
Resistance
100kΩ
R5
Resistance
4.7kΩ
R1
Resistance
400kΩ
R8
Resistance
11kΩ
J3
U7
U10
TP2
TP3
U9
L3
Inductance
10uH
L1
TP4
TP5
U8
D1
L4
Inductance
1.5 nH
L2
Inductance
10uH
TP1

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Project Specification — Project Aura Hearing Device
Project Overview
  • Status: Draft / corrected architecture selected; schematic capture may proceed after final part/pinout sourcing.
  • Device: Left-ear prototype of a custom BLE hearing-device/IEM system with an over-ear electronics hook and an in-ear multi-driver body.
  • Goal: Personal hearing correction, BLE audio/control, onboard recording, per-ear DSP, and prototype validation.
Intended Use
  • R&D prototype for bench and acoustic-coupler validation before any in-ear use.
  • Not production-intent and not medically certified.
  • Must include hearing-safety limits before wearable testing.
What the Device Should Do
  • Capture ambient audio through two hook microphones.
  • Run BLE audio/control and high-level audio handling on the nRF5340.
  • Use a Cirrus Logic CS47L63 audio DSP/front-end to bridge the nRF5340 stereo I2S stream into a multichannel downstream audio stream.
  • Use the CS47L63 onboard DSP to share hearing-correction / filtering load where practical.
  • Store profiles and recordings in external QSPI flash.
  • Communicate with a phone over BLE / BLE Audio.
  • Recharge from USB-C and support firmware update/debug access.
  • Drive a multi-BA in-ear acoustic assembly through one downstream digital Class-D amp per BA branch.
Main Features
  • nRF5340-CLAA-R BLE SoC, WLCSP95.
  • Cirrus Logic CS47L63-CWZR audio DSP/front-end, WLCSP61.
  • Three Analog Devices / Maxim MAX98360AEFB+ mono digital-input Class-D amplifiers, one per BA branch.
  • nPM1100 PMIC/charger concept.
  • W25Q01JV 1 Gbit QSPI NOR flash concept.
  • 32 MHz crystal and 2.4 GHz chip antenna concept.
  • Hook microphones: 2× TDK InvenSense ICS-40730 analog differential MEMS microphones, 74 dB SNR target.
  • USB-C charging and firmware access.
  • SWD test pads for recovery/debug.
  • Removable 3.7 V 150 mAh LiPo prototype battery via JST-PH.
  • Triple balanced-armature IEM concept: WBFK woofer, CI mid, TWFK dual tweeter.
Corrected System Architecture

Diagram


USB-C 5 V nPM1100 PMIC / charger 3.7 V LiPo Battery reverse / current protection 3.0 V system rail nRF5340 BLE SoC CS47L63 audio DSP / codec MAX98360A woofer amp MAX98360A mid amp MAX98360A tweeter amp QSPI NOR flash 2x ICS-40730 hook analog differential mics RF match + 2.4 GHz antenna WBFK woofer BA CI mid BA TWFK tweeter BA SWD pads
Hardware Subsystems
Power
  • USB-C provides 5 V input.
  • LiPo battery is removable for v0.1 prototyping.
  • Reverse-polarity protection is mandatory before the PMIC battery input.
  • PMIC rail current capability must be validated against SoC, flash, mics, CS47L63, and three MAX98360A audio amps.
  • Add USB-C CC pull-downs, ESD, VBUS protection, and no-backfeed safeguards.
Compute / Wireless
  • nRF5340 handles BLE, storage control, USB DFU strategy, system control, and host-side audio streaming.
  • CS47L63 handles audio front-end / DSP duties and expands the nRF5340 stereo I2S interface into the downstream multichannel audio path.
  • WLCSP + chip antenna is high RF/assembly risk for first revision; reference layout or module should be considered.
Microphones
  • Hook microphones are specified as 2× TDK InvenSense ICS-40730 analog differential MEMS microphones.
  • The ICS-40730 is not currently available in the Flux library and will require part creation/import or substitution before exact schematic capture.
  • Earlier PDM hook-mic assumptions are superseded by the ICS-40730 analog-differential mic decision.
  • Whether the IEM body still needs a local reference/feedback microphone remains an open system requirement unless explicitly removed.
Audio Output
  • Previous MAX98306 architecture is rejected.
  • Corrected path: nRF5340 stereo I2S into CS47L63; CS47L63 routes/processes audio and emits a multichannel digital ASP/TDM stream to three MAX98360A mono amplifiers.
  • The MAX98360A is a digital PCM/I2S/TDM input amplifier. It must not be driven from the CS47L63 analog OUTP/OUTN headphone output.
  • The CS47L63 analog output is mono differential OUTP/OUTN and is not the three-channel BA drive path.
  • MAX98360A TDM mode requires an 8-channel frame with 16-bit or 32-bit slots. Three amps can select different slots using DAI configuration plus GAIN_SLOT strapping.
Flex Interconnect
  • User decision: 7 conductors.
  • If CS47L63 and the three MAX98360A amps are in the IEM body, a 7-conductor flex can carry the hook-to-IEM digital/control link as: 3V0, GND, I2S_BCLK, I2S_FSYNC/LRCLK, I2S_DOUT, I2C_SCL, I2C_SDA.
  • This leaves no spare conductor for reset, interrupt, MCLK, shield, or extra ground; schematic capture must verify CS47L63 clocking/reset strategy before finalizing the connector pinout.
  • If the CS47L63 remains in the hook instead of the IEM body, the 7-conductor flex must be revisited because the downstream multichannel TDM or amplifier signals would cross the flex.
Interfaces and Connections
  • USB-C: VBUS, GND, D+, D-, CC1, CC2, shield strategy.
  • Battery: BAT+, BAT-, protected LiPo requirement, polarity marking.
  • SWD: SWDIO, SWDCLK, GND, optional VREF/VCC, 100 ohm series resistors.
  • Flash: QSPI SCK, CS, IO0-IO3, power, ground, hold/write-protect biasing as required.
  • CS47L63 control: I2C preferred for 7-conductor flex economy; SPI would require more conductors unless colocated with nRF5340.
  • nRF5340 to CS47L63 audio: stereo I2S / ASP link.
  • CS47L63 to MAX98360A amps: local 8-slot TDM digital audio bus with one slot selected per amp.
Power and Runtime Expectations
  • Battery: 3.7 V nominal, 150 mAh pouch cell prototype.
  • Runtime target is not yet validated; full power budget is required before PMIC/regulator commitment.
  • Charge current must be conservative for 150 mAh cell and thermal limits.
  • Audio output must be disabled or limited during USB attach/DFU unless validated.
Power Tree and Power Budget
  • Initial power tree is conceptual only.
  • Required next step: current budget for nRF5340 active/radio/DSP, CS47L63, three MAX98360A amps at expected SPL, flash read/write/erase, microphones, PMIC losses, USB charging, and sleep mode.
Library / Sourcing Status
  • Found in Flux library: CS47L63-CWZR, MAX98360AEFB+T / MAX98360AEFB+, NRF5340-CLAA-R7, NPM1100-QDAA-R7, W25Q01JVZEIQ, USB4125-GF-A, SPH0641LM4H-1, BAT54 variants.
  • Not found in Flux library: TDK InvenSense ICS-40730, Knowles WBFK-30095-000, Knowles CI-22955-000, Knowles TWFK-30017-000, exact 32 MHz 2.0×1.6 mm crystal, exact 7-pin 0.5 mm FFC/FPC connector.
  • A 7-pin exact flex connector may need a specific MPN; the library has similar 0.5 mm FFC/FPC connectors at higher pin counts.
Manufacturing and Assembly Expectations
  • Prototype v0.1 left ear only.
  • Rigid-flex PCB is expected eventually, but first electrical prototype may benefit from a larger rigid validation board.
  • WLCSP assembly and RF tuning are high risk.
  • Include test pads for power rails, SWD, USB, I2S/TDM/flex, I2C, mic outputs, and audio outputs.
Firmware-Relevant Hardware Requirements
  • Boot/DFU entry button on GPIO P0.11 concept.
  • USB DFU behavior must be validated for nRF5340 and PMIC port-detect timing.
  • SWD recovery pads are mandatory.
  • Zephyr / nRF Connect SDK support exists for CS47L63 in the nRF5340 Audio DK ecosystem, but custom routing to three MAX98360A amps may require devicetree/driver/audio-routing work.
  • Firmware must implement hard output gain limits, startup mute, watchdog/mute policy, and no full-scale audio test defaults.
Physical Design Expectations
  • Over-ear hook module contains battery, USB-C, SoC, PMIC, antenna, flash, hook microphones, and debug pads.
  • IEM body should contain CS47L63, three MAX98360A amps, acoustic drivers, and any local reference microphone if retained, so the 7-conductor flex carries only power, I2C, and nRF-to-CS47L63 audio.
  • Antenna keepout and battery/enclosure proximity must be defined before PCB layout.
Important Design Decisions
  • CS47L63 audio front-end selected to resolve nRF5340 native multichannel/TDM limitation.
  • Use CS47L63 digital ASP/TDM output, not its analog headphone output, to feed MAX98360A amps.
  • Keep flex cable at 7 conductors only if CS47L63 and amps are located in the IEM body and I2C control is acceptable.
  • Add battery reverse-polarity protection for prototype safety.
  • Add hearing-safety constraints before any in-ear test.
Assumptions
  • Current project is left-ear prototype only.
  • User-provided component list is a concept BOM, not yet fully validated.
  • The uploaded images are treated as v0.1 architecture sketches, not final schematics.
  • CS47L63 will be placed on the IEM-side electronics if the 7-conductor flex remains fixed.
Change Notes
  • 2026-07-15: Requirements extracted from uploaded concept text/images. Architecture review found blocking issues in audio amp compatibility and flex conductor count.
  • 2026-07-16: Updated architecture to nRF5340 → CS47L63 → 3× MAX98360A → three BA branches; retained 7-conductor flex and 2× ICS-40730 hook microphones; added sourcing status and digital-TDM-only constraint for MAX98360A.
  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • Corrected System Architecture

  • Hardware Subsystems

  • Power

  • Compute / Wireless

  • Microphones

  • Audio Output

  • Flex Interconnect

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Library / Sourcing Status

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions

  • Change Notes

Project Aura Hearing Device

Project Aura Hearing Device thumbnail
Left-ear prototype for Project Aura: a BLE hearing-device/IEM concept with nRF5340 compute, rechargeable LiPo power, digital microphones, flash storage, USB-C, and a multi-driver in-ear body. Current status: requirements captured; schematic capture is blocked pending audio/flex architecture correction.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$66.80–$74.29

Digi-Key

$16.60

HQonline

$1.65

LCSC

$82.52

Mouser

$61.56

TME

$0.22

Verical

$19.92–$30.08

Controls