Aurora Hearing Device Design
Worked for 29 sec
Blocked: your account is currently out of ACUs, so I can’t mutate the board/layout further in this run.
Accomplished this session:
- Started the 12 mm product-like redesign workflow.
- Loaded the required layout/component procedures for the crescent board, compact part replacement, and placement constraints.
- Confirmed the next execution plan: 12 mm max-width smooth crescent, 4-layer stackup, compact USB-C replacement, high-SPL mic replacement, removal/shrinking of bulky hook-side parts, and dense two-sided placement.
Remaining:
- Apply the new 12 mm crescent board outline and 4-layer stackup.
- Replace/flag oversized parts: current USB-C, ICS-40730 mics, large flash, tactile switch, and bulky connectors.
- Re-place the hook PCB components into the slim crescent form factor.
- Run layout fit/congestion checks and update the project documentation.
Estimate the ACUs needed to finish the 12 mm redesign.
Thought for 5 sec
Estimate: ~25–45 ACUs to finish a credible 12 mm hook redesign pass.
Breakdown:
- Apply 12 mm crescent outline + 4-layer stackup: 2–5 ACUs
- Research/replace compact USB-C + high-SPL mics + smaller flash/switch/connectors: 6–12 ACUs
- Re-place dense two-sided hook layout: 8–15 ACUs
- Fit/congestion/layout verification: 4–8 ACUs
- Update project docs and next-step notes: 2–5 ACUs
If we also route the board afterward, budget another 40–90 ACUs, because fine-pitch nRF5340/CS47L63, RF, USB, and dense wearable placement will likely need multiple iterations.
Proceed after ACUs
Prioritize fit check
Research compact parts
Update migration plan
Review power impact
Refine this doc
Ask about this doc
Power Budget and Rail Plan — Project Aura
Status
Draft / schematic-stage budget. Values are based on accessible datasheet data plus explicit engineering allocations where public active-mode data is unavailable.
Key Rail Decision
The original concept of using only the nPM1100 150 mA buck for the full 3.0 V system rail is too tight for a robust prototype. The schematic rail plan is revised as follows:
- nPM1100: LiPo charger / VSYS power-path source.
- TLV62568: dedicated 3.0 V, 1 A synchronous buck from VSYS.
- TPS79318-EP: 1.8 V low-noise LDO from 3V0 for CS47L63 analog rail.
- TLV70012: 1.2 V LDO from 3V0 for CS47L63 digital/core rail.
- MAX98360A amplifiers: powered from VSYS/battery, not the 3V0 rail.
Rail Summary
Table
| Rail | Source | Loads | Design Limit / Notes |
|---|---|---|---|
| VSYS | nPM1100 system rail / LiPo / USB power path | TLV62568 input, 3x MAX98360A VDD | nPM1100 battery/VSYS path supports up to about 660 mA battery-source current; USB input limited by 100 mA or 500 mA mode. |
| 3V0 | TLV62568 1 A buck | nRF5340, W25Q01JV, MIC1/MIC2, CS47L63 VDD_IO, 1V8/1V2 LDO inputs, flex 3V0 | Sized for flash current peaks and codec/mcu load margin. |
| 1V8_A | TPS79318-EP LDO | CS47L63 VDD_A | Low-noise rail; exact CS47L63 analog current must be measured because public datasheet does not expose a full active-current table. |
| 1V2_D | TLV70012 LDO | CS47L63 VDD_D | Core/FLL rail; exact active DSP current must be measured. |
Load Budget
3V0 Rail Loads
Table
| Load | Sleep / Standby | Typical / Expected | Peak / Design Budget | Evidence / Note |
|---|---|---|---|---|
| nRF5340 | ~1–3 uA System ON/OFF class states | ~9–12 mA BLE audio/control active allocation | 25 mA | Nordic current scenarios show combined CPU+radio examples around 9.9 mA typical at +3 dBm; LDO-mode and feature overlap can be higher. |
| W25Q01JV QSPI flash | 10 uA typ standby, 170 uA max standby | 20–30 mA program/erase class allocation | 100 mA read max at high-speed quad mode | Winbond datasheet: read max up to 100 mA at 133 MHz; program/erase typ 20 mA, max 25–50 mA depending mode. |
| 2x ICS-40730 | off if unpowered | ~0.57 mA | ~1 mA | TDK product data: ~285 uA each typical. |
| CS47L63 VDD_IO | unknown | 2–5 mA allocation | 10 mA allocation | Public Cirrus datasheet provides rail voltage but no complete active current table. |
| TPS79318 input for 1V8_A | off if disabled | 10–20 mA allocation + 0.17 mA IQ | 50 mA regulator budget | Actual CS47L63 analog current requires measurement; LDO rated 200 mA. |
| TLV70012 input for 1V2_D | off if disabled | 10–20 mA allocation + 0.031 mA IQ | 50 mA regulator budget | Actual CS47L63 digital/core current requires measurement; LDO rated 200 mA. |
| Pull-ups / leakage / margin | — | <1 mA | 5 mA | I2C pull-ups and leakage. |
Estimated 3V0 typical active load: ~55–90 mA depending flash and CS47L63 mode.
Estimated 3V0 peak design load: ~190–240 mA if high-speed flash read, radio/CPU, and codec/DSP current overlap.
Selected regulator: TLV62568, 1 A capable, so the 3V0 rail has sufficient current margin.
VSYS Loads
Table
| Load | Typical / Expected | Peak / Design Budget | Note |
|---|---|---|---|
| TLV62568 input | 3V0 load reflected through buck | ~180–260 mA input at low VSYS for 200–250 mA 3V0 rail load | Use worst-case low battery for input-current verification. |
| 3x MAX98360A quiescent | ~6.6 mA total at 3.7 V | ~10 mA max quiescent allocation | Datasheet: ~2.2 mA typ at 3.7 V, 2.85 mA max per amp. |
| 3x MAX98360A playback | SPL-limited; target should be milliwatt-class or lower into BA loads | Firmware/hardware must prevent high-power operation | MAX98360A can deliver far more power than safe for BA receivers. Do not size for full speaker-output power as a wearable operating point. |
Regulator / Protection Sizing
TLV62568 3V0 Buck
- VIN: VSYS, nominal LiPo/USB system rail.
- VOUT: 3.0 V.
- Datasheet feedback equation: VOUT = 0.6 V × (1 + R_TOP / R_BOTTOM).
- Selected divider: R_TOP = 400 kΩ, R_BOTTOM = 100 kΩ, giving 3.0 V nominal.
- Inductor: 2.2 uH shielded inductor, selected current rating 2.6 A.
- Input capacitor: 4.7 uF ceramic.
- Output capacitor: 10 uF ceramic.
- Optional feed-forward capacitor: 6.8 pF across feedback top resistor.
CS47L63 Rails
- VDD_IO: 3V0, to match nRF5340 GPIO/I2S/I2C logic.
- VDD_A: 1V8_A from TPS79318-EP low-noise LDO.
- VDD_D: 1V2_D from TLV70012 LDO.
- CS47L63 public datasheet does not provide a complete active current table; measurement on prototype is mandatory.
MAX98360A Amplifier Rails
- VDD: VSYS/battery, not 3V0.
- EN pins should be firmware-controlled or tied to a safe mute/enable policy.
- Add local decoupling and bulk capacitance near the amp cluster.
- Firmware must enforce startup mute, gain limits, and SPL limits.
Runtime Estimate
Because audio output power and CS47L63 active DSP current are not yet bounded by public datasheet data, runtime is only a rough range:
- 150 mAh cell at 3.7 V gives ~555 mWh nominal.
- Low/audio-control active estimate, 25–50 mA from battery-equivalent: ~3–6 hours.
- Heavier BLE + codec + flash + audio estimate, 75–150 mA: ~1–2 hours.
- Full-power MAX98360A operation is not a valid wearable operating case and would be unsafe for hearing and battery/runtime.
Design Risks / Open Items
- Measure CS47L63 active current on 1V8_A and 1V2_D rails; public data is insufficient.
- Verify MAX98360A digital input thresholds when VDD is VSYS and logic is 3V0.
- Validate W25Q01JV actual current at intended QSPI clock/mode; high-speed max read current is large.
- Keep MAX98360A output power strictly limited for Knowles BA receivers.
- Add current-measurement jumpers or test pads for VSYS, 3V0, 1V8_A, 1V2_D, and amp supply branch.
- Validate thermal behavior during charging plus playback.
- The nPM1100 buck may remain unused or reserved; it is not the main 3V0 rail in the revised robust prototype plan.
Change Note
2026-07-16: Added dedicated TLV62568 3V0 buck after power-budget review showed nPM1100's 150 mA buck is marginal for nRF5340 + W25Q01JV + CS47L63 + microphones.
Status
Key Rail Decision
Rail Summary
Load Budget
3V0 Rail Loads
VSYS Loads
Regulator / Protection Sizing
TLV62568 3V0 Buck
CS47L63 Rails
MAX98360A Amplifier Rails
Runtime Estimate
Design Risks / Open Items
Change Note
