Aurora Hearing Device Design


Blocked: your account is currently out of ACUs, so I can’t mutate the board/layout further in this run.
Accomplished this session:
  • Started the 12 mm product-like redesign workflow.
  • Loaded the required layout/component procedures for the crescent board, compact part replacement, and placement constraints.
  • Confirmed the next execution plan: 12 mm max-width smooth crescent, 4-layer stackup, compact USB-C replacement, high-SPL mic replacement, removal/shrinking of bulky hook-side parts, and dense two-sided placement.
Remaining:
  • Apply the new 12 mm crescent board outline and 4-layer stackup.
  • Replace/flag oversized parts: current USB-C, ICS-40730 mics, large flash, tactile switch, and bulky connectors.
  • Re-place the hook PCB components into the slim crescent form factor.
  • Run layout fit/congestion checks and update the project documentation.
Estimate the ACUs needed to finish the 12 mm redesign.
Estimate: ~25–45 ACUs to finish a credible 12 mm hook redesign pass.
Breakdown:
  • Apply 12 mm crescent outline + 4-layer stackup: 2–5 ACUs
  • Research/replace compact USB-C + high-SPL mics + smaller flash/switch/connectors: 6–12 ACUs
  • Re-place dense two-sided hook layout: 8–15 ACUs
  • Fit/congestion/layout verification: 4–8 ACUs
  • Update project docs and next-step notes: 2–5 ACUs
If we also route the board afterward, budget another 40–90 ACUs, because fine-pitch nRF5340/CS47L63, RF, USB, and dense wearable placement will likely need multiple iterations.
Proceed after ACUs
Prioritize fit check
Research compact parts
Update migration plan
Review power impact

Y1
SPK1
U6
J1
ANT1
J2
U5
U4
SPK3
MIC2
End of Life
SPK2
U3
MIC1
End of Life
J1 VBUS - U6 VBUS
U1 P0.22 - U2 ASP2_DIN/GPIO6
U2 VREF1_FILT - C21 P1
U1 VDD_3 - U1 VDD_4
U2 AS[1_DOUT/GPIO1 - U3 DAI2
J1 CC2 - R4 P1
L4 P2 - ANT1 FEEDING_POINT
U1 DECN - C18 P1
U8 EN - C6 P1
U1 VDD_9 - U1 VDDH
U2 VREF1_FILT - C21 P1
U1 DCC - L2 P1
MIC2 OUTPUT+ - C26 P1
U1 P0.24 - U2 IRQ
L4 P2 - ANT1 FEEDING_POINT
U1 VDD_9 - U1 VDDH
U2 VREF2_FILT - C22 P1
U1 NRESET - TP3 P1
U5 OUTN - SPK3 TERMINAL_1
U1 VDD_9 - U1 VDDH
U1 VDD_9 - U1 VDDH
U1 VDD_9 - U1 VDDH
C25 P2 - U2 IN1LN_1
U6 VSYS - U10 VIN
U1 VDD_9 - U1 VDDH
U8 BP - C8 P1
U1 VDD_9 - U1 VDDH
MIC2 OUTPUT+ - C26 P1
C27 P2 - U2 IN2LN
L2 P2 - U1 DECR
J1 D- - U1 D-
U1 P0.25/AIN4 - U3 EN
U6 VSYS - U10 VIN
J1 CC1 - R3 P1
J1 D- - U1 D-
U3 OUTN - SPK1 COIL_A
U5 OUTP - SPK3 TERMINAL_2
U6 NTC - R9 P1
U7 DI_(IO0) - U1 P0.13/IO0
U1 P0.25/AIN4 - U3 EN
U9 OUT - C10 P1
MIC1 OUTPUT- - C25 P1
U6 DEC - C23 P1
U1 P1.03/TWI - U2 SPI1_MOSI/I2C1_SDA
C24 P2 - U2 IN1LP_1
U1 P0.23 - U2 RESET
U1 P1.02/TWI - U2 SPI1_MISO/I2C1_SCL
U1 P0.25/AIN4 - U3 EN
J1 D+ - U1 D+
J3 1 - D1 A
U1 P0.21 - U2 ASP2_FSYNC/GPIO8
U6 VSYS - U10 VIN
U1 VDD_9 - U1 VDDH
U1 ANT - L4 P1
U9 OUT - C10 P1
L3 P2 - U1 DECD
U8 BP - C8 P1
U3 OUTP - SPK1 COIL_B
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U1 P0.23 - U2 RESET
U1 VDD_3 - U1 VDD_4
U9 EN - C9 P1
U7 ~WP_(IO2) - U1 P0.15/IO2
U3 OUTP - SPK1 COIL_B
U10 FB - R1 P2
U1 VDD_3 - U1 VDD_4
U7 ~WP_(IO2) - U1 P0.15/IO2
MIC1 OUTPUT- - C25 P1
U1 XC1 - Y1 XTAL1
U1 DECN - C18 P1
U7 DO_(IO1) - U1 P0.14/IO1
U1 P0.25/AIN4 - U3 EN
U6 VSYS - U10 VIN
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U2 AS[1_DOUT/GPIO1 - U3 DAI2
U1 XC2 - Y1 XTAL2
U1 XC2 - Y1 XTAL2
U7 ~HOLD_OR_~RESET_(IO3) - U1 P0.16/IO3
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U1 SWDIO - TP1 P1
MIC2 OUTPUT- - C27 P1
L4 P2 - ANT1 FEEDING_POINT
U1 P0.25/AIN4 - U3 EN
U1 DECUSB - C20 P1
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U6 VSYS - U10 VIN
U10 SW - L1 1
U7 ~CS - U1 P0.18/CSN
J1 CC2 - R4 P1
J1 VBUS - U6 VBUS
U7 CLK - U1 P0.17/SCK
U1 DECRF - C15 P1
U6 VSYS - U10 VIN
U1 VDD_9 - U1 VDDH
U1 P0.24 - U2 IRQ
U6 VSYS - U10 VIN
U1 P0.11/TRACEDATA0/CSN - SW1 1
U1 VDD_9 - U1 VDDH
J1 D+ - U1 D+
U1 VDD_9 - U1 VDDH
U2 AS[1_DOUT/GPIO1 - U3 DAI2
U3 OUTN - SPK1 COIL_A
C24 P2 - U2 IN1LP_1
U1 DECA - C19 P1
U6 NTC - R9 P1
U1 XC2 - Y1 XTAL2
U6 VSYS - U10 VIN
U6 DEC - C23 P1
C26 P2 - U2 IN2LP
U1 VDD_9 - U1 VDDH
U1 P1.02/TWI - U2 SPI1_MISO/I2C1_SCL
J3 1 - D1 A
U1 XC1 - Y1 XTAL1
U9 EN - C9 P1
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U1 P1.03/TWI - U2 SPI1_MOSI/I2C1_SDA
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U1 DCCD - L3 P1
U1 VDD_1 - U1 VDD_2
U1 DCC - L2 P1
L3 P2 - U1 DECD
U5 OUTP - SPK3 TERMINAL_2
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U4 OUTN - SPK2 N
U4 OUTN - SPK2 N
U9 OUT - C10 P1
U1 P0.21 - U2 ASP2_FSYNC/GPIO8
D1 K - U6 VBAT
J1 VBUS - U6 VBUS
U1 P0.25/AIN4 - U3 EN
U1 DECRF - C15 P1
J1 CC1 - R3 P1
U4 OUTP - SPK2 P
U9 OUT - C10 P1
U6 VSYS - U10 VIN
U2 AS[1_DOUT/GPIO1 - U3 DAI2
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U1 DCCD - L3 P1
C27 P2 - U2 IN2LN
U2 VREF2_FILT - C22 P1
U1 P0.11/TRACEDATA0/CSN - SW1 1
J1 D- - U1 D-
U6 ICHG - R8 P1
U1 P1.03/TWI - U2 SPI1_MOSI/I2C1_SDA
MIC1 OUTPUT+ - C24 P1
U1 VDD_9 - U1 VDDH
U1 XC1 - Y1 XTAL1
U10 SW - L1 1
U1 SWDIO - TP1 P1
U5 OUTN - SPK3 TERMINAL_1
U1 ANT - L4 P1
L2 P2 - U1 DECR
MIC1 OUTPUT+ - C24 P1
C25 P2 - U2 IN1LN_1
U2 AS[1_DOUT/GPIO1 - U3 DAI2
U1 DECRF - C15 P1
U1 P0.20 - U2 ASP2_BCLK/GPIO7
U6 VSYS - U10 VIN
MIC2 OUTPUT- - C27 P1
U4 OUTP - SPK2 P
U1 DECA - C19 P1
U1 VDD_9 - U1 VDDH
J1 D+ - U1 D+
U10 FB - R1 P2
U7 DI_(IO0) - U1 P0.13/IO0
U8 OUT - C7 P1
U1 SWDCLK - TP2 P1
C26 P2 - U2 IN2LP
U1 VDD_3 - U1 VDD_4
D1 K - U6 VBAT
U1 P1.02/TWI - U2 SPI1_MISO/I2C1_SCL
U8 EN - C6 P1
U6 ICHG - R8 P1
U6 VSYS - U10 VIN
U1 P0.22 - U2 ASP2_DIN/GPIO6
U1 ANT - L4 P1
U1 VDD_3 - U1 VDD_4
U10 FB - R1 P2
L3 P2 - U1 DECD
U6 VSYS - U10 VIN
U6 VSYS - U10 VIN
U8 EN - C6 P1
U8 OUT - C7 P1
U1 NRESET - TP3 P1
U1 P0.20 - U2 ASP2_BCLK/GPIO7
U8 OUT - C7 P1
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U1 VDD_1 - U1 VDD_2
U7 DO_(IO1) - U1 P0.14/IO1
U7 ~HOLD_OR_~RESET_(IO3) - U1 P0.16/IO3
U1 DECUSB - C20 P1
U1 VDD_9 - U1 VDDH
U10 FB - R1 P2
U1 VDD_9 - U1 VDDH
U7 CLK - U1 P0.17/SCK
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U6 VSYS - U10 VIN
U1 VDD_3 - U1 VDD_4
U7 ~CS - U1 P0.18/CSN
U1 SWDCLK - TP2 P1
C7 P2 - C8 P2
U6 AVSS_EP - U6 PVSS
C15 P2 - C16 P2
GND
R8 P2 - U6 ISET
U1 VSS_4 - U1 VSS_5
C7 P2 - C8 P2
U10 GND - C2 P2
C15 P2 - C16 P2
U10 GND - C2 P2
R8 P2 - U6 ISET
R8 P2 - U6 ISET
C30 P2 - C31 P2
U6 AVSS_EP - U6 PVSS
U1 AVSS_3 - U2 GND_A
J1 GND - R3 P2
U2 GND_D - U2 GND_SUB
U10 GND - C2 P2
R8 P2 - U6 ISET
Y1 GND - C4 P2
U2 GND_D - U2 GND_SUB
C21 P2 - C22 P2
ANT1 GND_2 - U2 VDD_LDO
C15 P2 - C16 P2
R7 P2 - U3 GAIN_SLOT
U1 AVSS_1 - U1 AVSS_2
R8 P2 - U6 ISET
J1 GND - R3 P2
U1 VSS_12 - U1 VSS_13
C15 P2 - C16 P2
U1 AVSS_3 - U2 GND_A
GND
U6 AVSS_EP - U6 PVSS
U5 GND_2 - J2 GND
R8 P2 - U6 ISET
C28 P2 - C29 P2
U1 AVSS_3 - U2 GND_A
U1 VSS_4 - U1 VSS_5
Y1 GND - C4 P2
U1 VSS_12 - U1 VSS_13
C7 P2 - C8 P2
U2 GND_D - U2 GND_SUB
ANT1 GND_2 - U2 VDD_LDO
R8 P2 - U6 ISET
U6 AVSS_EP - U6 PVSS
GND
U2 GND_D - U2 GND_SUB
C30 P2 - C31 P2
U10 GND - C2 P2
Y1 GND - C4 P2
U6 AVSS_EP - U6 PVSS
C21 P2 - C22 P2
U6 AVSS_EP - U6 PVSS
R8 P2 - U6 ISET
C15 P2 - C16 P2
U2 GND_D - U2 GND_SUB
U1 AVSS_3 - U2 GND_A
U10 GND - C2 P2
C15 P2 - C16 P2
C28 P2 - C29 P2
C21 P2 - C22 P2
GND
U1 AVSS_3 - U2 GND_A
R7 P2 - U3 GAIN_SLOT
U6 AVSS_EP - U6 PVSS
R8 P2 - U6 ISET
U6 AVSS_EP - U6 PVSS
C28 P2 - C29 P2
J1 GND - R3 P2
U10 GND - C2 P2
U5 GND_2 - J2 GND
U2 GND_D - U2 GND_SUB
U1 AVSS_1 - U1 AVSS_2
U10 GND - C2 P2
C31
Capacitance
DNP F
C8
Capacitance
0.01uF
C26
Capacitance
2.2 µF
C24
Capacitance
2.2 µF
C20
Capacitance
100nF
C13
Capacitance
1uF
C3
Capacitance
6.8pF
C9
Capacitance
1uF
C5
Capacitance
12pF
C28
Capacitance
0.1 µF
C21
Capacitance
2.2uF
C27
Capacitance
2.2 µF
C30
Capacitance
DNP F
C22
Capacitance
10uF
C10
Capacitance
1uF
C18
Capacitance
100nF
C12
Capacitance
1uF
C23
Capacitance
10uF
C19
Capacitance
1uF
C14
Capacitance
10uF
C1
Capacitance
4.7uF
C2
Capacitance
10uF
C15
Capacitance
1uF
C25
Capacitance
2.2 µF
C29
Capacitance
0.1 µF
C6
Capacitance
0.1uF
C4
Capacitance
12pF
C16
Capacitance
2.2nF
C7
Capacitance
2.2uF
C17
Capacitance
1uF
C11
Capacitance
1uF
U1
R9
Resistance
10kΩ
R4
Resistance
5.1kΩ
R6
Resistance
4.7kΩ
R2
Resistance
100kΩ
R3
Resistance
5.1kΩ
R7
Resistance
100kΩ
R5
Resistance
4.7kΩ
R1
Resistance
400kΩ
R8
Resistance
11kΩ
SW1
U2
J3
U7
U10
TP2
TP3
U9
L3
Inductance
10uH
TP4
TP5
L4
Inductance
1.5 nH
L2
Inductance
10uH
TP1
L1
U8
D1
Architecture Review Notes — Project Aura
Current Resolution Summary
The previous audio architecture blocker is resolved by adding a Cirrus Logic CS47L63 audio DSP/front-end between the nRF5340 and the downstream balanced-armature driver chain.
Corrected high-level path:

Diagram


nRF5340 DSP A1 WBFK BA woofer A2 CI BA mid A3 TWFK BA tweeter
Resolved Findings
ERR-001 — MAX98306 audio-path mismatch
  • Status: Resolved by removing MAX98306 from the architecture.
  • Replacement architecture uses CS47L63 plus three MAX98360A digital-input mono Class-D amps.
ERR-004 — nRF5340 native TDM / 3-channel audio limitation
  • Status: Resolved conceptually by the CS47L63.
  • CS47L63 provides two audio serial ports. Datasheet evidence: ASP1 supports up to eight input/output channels; ASP2 supports up to four input/output channels; I2S and TDM modes are supported.
  • nRF5340 can send stereo I2S to CS47L63, and the CS47L63 can emit a multichannel digital stream for the downstream amps.
ERR-005 — MAX98360A 8-slot TDM requirement
  • Status: Resolved if the MAX98360A amps are driven from a CS47L63 digital ASP/TDM output.
  • MAX98360A TDM mode accepts 8 channels only, with 16-bit or 32-bit slots and exactly 128 or 256 BCLK cycles per frame.
  • Three amps can select different TDM slots using DAI configuration plus GAIN_SLOT strapping.
Important Compatibility Constraint
The CS47L63 must feed the MAX98360A amps through a digital audio serial port, not through the CS47L63 analog headphone output.
  • CS47L63 analog output: mono differential OUTP/OUTN headphone/earpiece path.
  • MAX98360A input: digital PCM/I2S/TDM only; no analog input.
  • Therefore the valid path is: CS47L63 ASP_DOUT + BCLK + FSYNC to MAX98360A DAI pins.
  • Invalid path: CS47L63 OUTP/OUTN analog output into MAX98360A.
Flex Cable Decision
User decision
  • Flex cable pin count remains 7 conductors.
Viable 7-conductor interpretation
This is viable only if the CS47L63 and three MAX98360A amps are placed in the IEM-side electronics, so the flex carries the upstream hook-to-IEM link rather than the local multichannel amp bus.
Candidate 7-conductor pinout:

Table


PinSignal
13V0
2GND
3I2S_BCLK from nRF5340
4I2S_FSYNC / LRCLK from nRF5340
5I2S_DOUT from nRF5340 to CS47L63
6I2C_SCL
7I2C_SDA
Risks of 7 conductors
  • No spare conductor for CS47L63 RESET, IRQ, MCLK, amplifier enable, cable detect, shield, or extra ground.
  • I2C is strongly preferred over SPI because SPI control would consume too many conductors.
  • CS47L63 clocking/reset/interrupt requirements must be checked during schematic capture.
  • If CS47L63 is placed in the hook instead of the IEM body, the 7-conductor flex becomes insufficient again for a robust multichannel downstream audio/power/control interface.
Microphone Decision
Hook microphones
  • User decision: 2× TDK InvenSense ICS-40730 analog differential MEMS microphones, 74 dB SNR target.
  • These are independent of the downstream amp architecture.
  • Flux library status: not currently found; requires part creation/import, user-supplied library, or substitution.
IEM reference microphone
  • The previous concept included an IEM-body SPH0641LM4H-1 PDM reference microphone.
  • The latest user correction only explicitly resolves the hook microphones, so the IEM reference/feedback mic remains an open requirement unless removed.
Library Availability Snapshot
Found in Flux library:

Table


FunctionPartStatus
Audio DSP/front-endCS47L63-CWZRFound
Digital mono ampMAX98360AEFB+T / MAX98360AEFB+Found
BLE SoCNRF5340-CLAA-R7Found
PMIC/chargerNPM1100-QDAA-R7Found
QSPI flashW25Q01JVZEIQFound
USB-C receptacleUSB4125-GF-AFound
Legacy/reference PDM micSPH0641LM4H-1Found
Schottky diodeBAT54 variantsFound
Not found or not exact:

Table


FunctionPartStatus
Hook analog differential micTDK InvenSense ICS-40730Not found
BA wooferKnowles WBFK-30095-000Not found
BA midKnowles CI-22955-000Not found
BA tweeterKnowles TWFK-30017-000Not found
HF crystalexact 32 MHz 2.0×1.6 mm crystalNot found without MPN
Flex connectorexact 7-pin 0.5 mm FFC/FPC connectorNot found; similar higher-pin-count parts exist
Remaining Architecture Risks
1. CS47L63 firmware/audio-routing complexity
  • Nordic/Zephyr ecosystem support exists for CS47L63, but custom routing from stereo I2S input to three downstream MAX98360A slot outputs may require nontrivial codec/DSP configuration.
  • Schematic should include test pads on ASP/I2S/TDM signals for bring-up.
2. Audio safety and BA-driver suitability
  • MAX98360A is intended for small speaker loads and can deliver far more energy than safe for high-sensitivity balanced-armature receivers.
  • Hardware and firmware SPL limiting, startup mute, per-amp gain/slot validation, and acoustic-coupler testing are mandatory.
3. Power budget
  • The nPM1100 rail capacity must be validated with nRF5340, CS47L63, flash, two analog mics, and three Class-D amps.
  • A 150 mAh LiPo plus three amps may impose runtime and thermal limits.
4. RF/antenna and WLCSP risk
  • nRF5340 WLCSP plus chip antenna requires strict Nordic RF layout and tuning.
  • Ear, skin, battery, flex, and enclosure will detune the antenna.
  • Consider a certified module or larger validation board for first electrical prototype if schedule/risk matters.
5. Missing parts
  • ICS-40730 and Knowles BA receiver parts are absent from the Flux library.
  • Exact schematic capture for those devices requires importing/creating parts from datasheets or selecting library-available substitutes.
Proceed with schematic capture in this order:
  1. Add available core ICs: nRF5340, CS47L63, MAX98360A ×3, nPM1100, W25Q01JV, USB-C, SWD/test pads.
  2. Source or create the missing ICS-40730 and BA receiver parts from datasheets before placing those exact devices.
  3. Finalize CS47L63 placement in the IEM body if the 7-conductor flex remains fixed.
  4. Use I2C control across the flex; avoid SPI across the 7-conductor flex.
  5. Verify CS47L63 clocking/reset/IRQ requirements and whether any signal requires an eighth conductor.
  6. Add hearing-safety limits and test pads before layout.
Superseded Findings
The original findings below are no longer active blockers but remain historical context:
  • MAX98306 is not an I2S/3-channel amp.
  • nRF5340 cannot natively generate the required multichannel MAX98360A TDM stream.
  • A four-conductor flex is insufficient for the original mixed I2S/PDM plan.
  • Current Resolution Summary

  • Resolved Findings

  • ERR-001 — MAX98306 audio-path mismatch

  • ERR-004 — nRF5340 native TDM / 3-channel audio limitation

  • ERR-005 — MAX98360A 8-slot TDM requirement

  • Important Compatibility Constraint

  • Flex Cable Decision

  • User decision

  • Viable 7-conductor interpretation

  • Risks of 7 conductors

  • Microphone Decision

  • Hook microphones

  • IEM reference microphone

  • Library Availability Snapshot

  • Remaining Architecture Risks

  • 1. CS47L63 firmware/audio-routing complexity

  • 2. Audio safety and BA-driver suitability

  • 3. Power budget

  • 4. RF/antenna and WLCSP risk

  • 5. Missing parts

  • Recommended Next Design Direction

  • Superseded Findings