Aurora Hearing Device Design


Blocked: your account is currently out of ACUs, so I can’t mutate the board/layout further in this run.
Accomplished this session:
  • Started the 12 mm product-like redesign workflow.
  • Loaded the required layout/component procedures for the crescent board, compact part replacement, and placement constraints.
  • Confirmed the next execution plan: 12 mm max-width smooth crescent, 4-layer stackup, compact USB-C replacement, high-SPL mic replacement, removal/shrinking of bulky hook-side parts, and dense two-sided placement.
Remaining:
  • Apply the new 12 mm crescent board outline and 4-layer stackup.
  • Replace/flag oversized parts: current USB-C, ICS-40730 mics, large flash, tactile switch, and bulky connectors.
  • Re-place the hook PCB components into the slim crescent form factor.
  • Run layout fit/congestion checks and update the project documentation.
Estimate the ACUs needed to finish the 12 mm redesign.
Estimate: ~25–45 ACUs to finish a credible 12 mm hook redesign pass.
Breakdown:
  • Apply 12 mm crescent outline + 4-layer stackup: 2–5 ACUs
  • Research/replace compact USB-C + high-SPL mics + smaller flash/switch/connectors: 6–12 ACUs
  • Re-place dense two-sided hook layout: 8–15 ACUs
  • Fit/congestion/layout verification: 4–8 ACUs
  • Update project docs and next-step notes: 2–5 ACUs
If we also route the board afterward, budget another 40–90 ACUs, because fine-pitch nRF5340/CS47L63, RF, USB, and dense wearable placement will likely need multiple iterations.
Proceed after ACUs
Prioritize fit check
Research compact parts
Update migration plan
Review power impact

Y1
SPK1
U6
J1
ANT1
J2
U5
U4
SPK3
MIC2
End of Life
SPK2
U3
MIC1
End of Life
J1 VBUS - U6 VBUS
U1 P0.22 - U2 ASP2_DIN/GPIO6
U2 VREF1_FILT - C21 P1
U1 VDD_3 - U1 VDD_4
U2 AS[1_DOUT/GPIO1 - U3 DAI2
J1 CC2 - R4 P1
L4 P2 - ANT1 FEEDING_POINT
U1 DECN - C18 P1
U8 EN - C6 P1
U1 VDD_9 - U1 VDDH
U2 VREF1_FILT - C21 P1
U1 DCC - L2 P1
MIC2 OUTPUT+ - C26 P1
U1 P0.24 - U2 IRQ
L4 P2 - ANT1 FEEDING_POINT
U1 VDD_9 - U1 VDDH
U2 VREF2_FILT - C22 P1
U1 NRESET - TP3 P1
U5 OUTN - SPK3 TERMINAL_1
U1 VDD_9 - U1 VDDH
U1 VDD_9 - U1 VDDH
U1 VDD_9 - U1 VDDH
C25 P2 - U2 IN1LN_1
U6 VSYS - U10 VIN
U1 VDD_9 - U1 VDDH
U8 BP - C8 P1
U1 VDD_9 - U1 VDDH
MIC2 OUTPUT+ - C26 P1
C27 P2 - U2 IN2LN
L2 P2 - U1 DECR
J1 D- - U1 D-
U1 P0.25/AIN4 - U3 EN
U6 VSYS - U10 VIN
J1 CC1 - R3 P1
J1 D- - U1 D-
U3 OUTN - SPK1 COIL_A
U5 OUTP - SPK3 TERMINAL_2
U6 NTC - R9 P1
U7 DI_(IO0) - U1 P0.13/IO0
U1 P0.25/AIN4 - U3 EN
U9 OUT - C10 P1
MIC1 OUTPUT- - C25 P1
U6 DEC - C23 P1
U1 P1.03/TWI - U2 SPI1_MOSI/I2C1_SDA
C24 P2 - U2 IN1LP_1
U1 P0.23 - U2 RESET
U1 P1.02/TWI - U2 SPI1_MISO/I2C1_SCL
U1 P0.25/AIN4 - U3 EN
J1 D+ - U1 D+
J3 1 - D1 A
U1 P0.21 - U2 ASP2_FSYNC/GPIO8
U6 VSYS - U10 VIN
U1 VDD_9 - U1 VDDH
U1 ANT - L4 P1
U9 OUT - C10 P1
L3 P2 - U1 DECD
U8 BP - C8 P1
U3 OUTP - SPK1 COIL_B
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U1 P0.23 - U2 RESET
U1 VDD_3 - U1 VDD_4
U9 EN - C9 P1
U7 ~WP_(IO2) - U1 P0.15/IO2
U3 OUTP - SPK1 COIL_B
U10 FB - R1 P2
U1 VDD_3 - U1 VDD_4
U7 ~WP_(IO2) - U1 P0.15/IO2
MIC1 OUTPUT- - C25 P1
U1 XC1 - Y1 XTAL1
U1 DECN - C18 P1
U7 DO_(IO1) - U1 P0.14/IO1
U1 P0.25/AIN4 - U3 EN
U6 VSYS - U10 VIN
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U2 AS[1_DOUT/GPIO1 - U3 DAI2
U1 XC2 - Y1 XTAL2
U1 XC2 - Y1 XTAL2
U7 ~HOLD_OR_~RESET_(IO3) - U1 P0.16/IO3
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U1 SWDIO - TP1 P1
MIC2 OUTPUT- - C27 P1
L4 P2 - ANT1 FEEDING_POINT
U1 P0.25/AIN4 - U3 EN
U1 DECUSB - C20 P1
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U6 VSYS - U10 VIN
U10 SW - L1 1
U7 ~CS - U1 P0.18/CSN
J1 CC2 - R4 P1
J1 VBUS - U6 VBUS
U7 CLK - U1 P0.17/SCK
U1 DECRF - C15 P1
U6 VSYS - U10 VIN
U1 VDD_9 - U1 VDDH
U1 P0.24 - U2 IRQ
U6 VSYS - U10 VIN
U1 P0.11/TRACEDATA0/CSN - SW1 1
U1 VDD_9 - U1 VDDH
J1 D+ - U1 D+
U1 VDD_9 - U1 VDDH
U2 AS[1_DOUT/GPIO1 - U3 DAI2
U3 OUTN - SPK1 COIL_A
C24 P2 - U2 IN1LP_1
U1 DECA - C19 P1
U6 NTC - R9 P1
U1 XC2 - Y1 XTAL2
U6 VSYS - U10 VIN
U6 DEC - C23 P1
C26 P2 - U2 IN2LP
U1 VDD_9 - U1 VDDH
U1 P1.02/TWI - U2 SPI1_MISO/I2C1_SCL
J3 1 - D1 A
U1 XC1 - Y1 XTAL1
U9 EN - C9 P1
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U1 P1.03/TWI - U2 SPI1_MOSI/I2C1_SDA
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U1 DCCD - L3 P1
U1 VDD_1 - U1 VDD_2
U1 DCC - L2 P1
L3 P2 - U1 DECD
U5 OUTP - SPK3 TERMINAL_2
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U4 OUTN - SPK2 N
U4 OUTN - SPK2 N
U9 OUT - C10 P1
U1 P0.21 - U2 ASP2_FSYNC/GPIO8
D1 K - U6 VBAT
J1 VBUS - U6 VBUS
U1 P0.25/AIN4 - U3 EN
U1 DECRF - C15 P1
J1 CC1 - R3 P1
U4 OUTP - SPK2 P
U9 OUT - C10 P1
U6 VSYS - U10 VIN
U2 AS[1_DOUT/GPIO1 - U3 DAI2
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U1 DCCD - L3 P1
C27 P2 - U2 IN2LN
U2 VREF2_FILT - C22 P1
U1 P0.11/TRACEDATA0/CSN - SW1 1
J1 D- - U1 D-
U6 ICHG - R8 P1
U1 P1.03/TWI - U2 SPI1_MOSI/I2C1_SDA
MIC1 OUTPUT+ - C24 P1
U1 VDD_9 - U1 VDDH
U1 XC1 - Y1 XTAL1
U10 SW - L1 1
U1 SWDIO - TP1 P1
U5 OUTN - SPK3 TERMINAL_1
U1 ANT - L4 P1
L2 P2 - U1 DECR
MIC1 OUTPUT+ - C24 P1
C25 P2 - U2 IN1LN_1
U2 AS[1_DOUT/GPIO1 - U3 DAI2
U1 DECRF - C15 P1
U1 P0.20 - U2 ASP2_BCLK/GPIO7
U6 VSYS - U10 VIN
MIC2 OUTPUT- - C27 P1
U4 OUTP - SPK2 P
U1 DECA - C19 P1
U1 VDD_9 - U1 VDDH
J1 D+ - U1 D+
U10 FB - R1 P2
U7 DI_(IO0) - U1 P0.13/IO0
U8 OUT - C7 P1
U1 SWDCLK - TP2 P1
C26 P2 - U2 IN2LP
U1 VDD_3 - U1 VDD_4
D1 K - U6 VBAT
U1 P1.02/TWI - U2 SPI1_MISO/I2C1_SCL
U8 EN - C6 P1
U6 ICHG - R8 P1
U6 VSYS - U10 VIN
U1 P0.22 - U2 ASP2_DIN/GPIO6
U1 ANT - L4 P1
U1 VDD_3 - U1 VDD_4
U10 FB - R1 P2
L3 P2 - U1 DECD
U6 VSYS - U10 VIN
U6 VSYS - U10 VIN
U8 EN - C6 P1
U8 OUT - C7 P1
U1 NRESET - TP3 P1
U1 P0.20 - U2 ASP2_BCLK/GPIO7
U8 OUT - C7 P1
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U1 VDD_1 - U1 VDD_2
U7 DO_(IO1) - U1 P0.14/IO1
U7 ~HOLD_OR_~RESET_(IO3) - U1 P0.16/IO3
U1 DECUSB - C20 P1
U1 VDD_9 - U1 VDDH
U10 FB - R1 P2
U1 VDD_9 - U1 VDDH
U7 CLK - U1 P0.17/SCK
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U6 VSYS - U10 VIN
U1 VDD_3 - U1 VDD_4
U7 ~CS - U1 P0.18/CSN
U1 SWDCLK - TP2 P1
C7 P2 - C8 P2
U6 AVSS_EP - U6 PVSS
C15 P2 - C16 P2
GND
R8 P2 - U6 ISET
U1 VSS_4 - U1 VSS_5
C7 P2 - C8 P2
U10 GND - C2 P2
C15 P2 - C16 P2
U10 GND - C2 P2
R8 P2 - U6 ISET
R8 P2 - U6 ISET
C30 P2 - C31 P2
U6 AVSS_EP - U6 PVSS
U1 AVSS_3 - U2 GND_A
J1 GND - R3 P2
U2 GND_D - U2 GND_SUB
U10 GND - C2 P2
R8 P2 - U6 ISET
Y1 GND - C4 P2
U2 GND_D - U2 GND_SUB
C21 P2 - C22 P2
ANT1 GND_2 - U2 VDD_LDO
C15 P2 - C16 P2
R7 P2 - U3 GAIN_SLOT
U1 AVSS_1 - U1 AVSS_2
R8 P2 - U6 ISET
J1 GND - R3 P2
U1 VSS_12 - U1 VSS_13
C15 P2 - C16 P2
U1 AVSS_3 - U2 GND_A
GND
U6 AVSS_EP - U6 PVSS
U5 GND_2 - J2 GND
R8 P2 - U6 ISET
C28 P2 - C29 P2
U1 AVSS_3 - U2 GND_A
U1 VSS_4 - U1 VSS_5
Y1 GND - C4 P2
U1 VSS_12 - U1 VSS_13
C7 P2 - C8 P2
U2 GND_D - U2 GND_SUB
ANT1 GND_2 - U2 VDD_LDO
R8 P2 - U6 ISET
U6 AVSS_EP - U6 PVSS
GND
U2 GND_D - U2 GND_SUB
C30 P2 - C31 P2
U10 GND - C2 P2
Y1 GND - C4 P2
U6 AVSS_EP - U6 PVSS
C21 P2 - C22 P2
U6 AVSS_EP - U6 PVSS
R8 P2 - U6 ISET
C15 P2 - C16 P2
U2 GND_D - U2 GND_SUB
U1 AVSS_3 - U2 GND_A
U10 GND - C2 P2
C15 P2 - C16 P2
C28 P2 - C29 P2
C21 P2 - C22 P2
GND
U1 AVSS_3 - U2 GND_A
R7 P2 - U3 GAIN_SLOT
U6 AVSS_EP - U6 PVSS
R8 P2 - U6 ISET
U6 AVSS_EP - U6 PVSS
C28 P2 - C29 P2
J1 GND - R3 P2
U10 GND - C2 P2
U5 GND_2 - J2 GND
U2 GND_D - U2 GND_SUB
U1 AVSS_1 - U1 AVSS_2
U10 GND - C2 P2
C31
Capacitance
DNP F
C8
Capacitance
0.01uF
C26
Capacitance
2.2 µF
C24
Capacitance
2.2 µF
C20
Capacitance
100nF
C13
Capacitance
1uF
C3
Capacitance
6.8pF
C9
Capacitance
1uF
C5
Capacitance
12pF
C28
Capacitance
0.1 µF
C21
Capacitance
2.2uF
C27
Capacitance
2.2 µF
C30
Capacitance
DNP F
C22
Capacitance
10uF
C10
Capacitance
1uF
C18
Capacitance
100nF
C12
Capacitance
1uF
C23
Capacitance
10uF
C19
Capacitance
1uF
C14
Capacitance
10uF
C1
Capacitance
4.7uF
C2
Capacitance
10uF
C15
Capacitance
1uF
C25
Capacitance
2.2 µF
C29
Capacitance
0.1 µF
C6
Capacitance
0.1uF
C4
Capacitance
12pF
C16
Capacitance
2.2nF
C7
Capacitance
2.2uF
C17
Capacitance
1uF
C11
Capacitance
1uF
U1
R9
Resistance
10kΩ
SW1
R4
Resistance
5.1kΩ
R6
Resistance
4.7kΩ
R2
Resistance
100kΩ
R3
Resistance
5.1kΩ
R7
Resistance
100kΩ
R5
Resistance
4.7kΩ
R1
Resistance
400kΩ
R8
Resistance
11kΩ
U2
U7
J3
U10
TP2
TP3
U9
L3
Inductance
10uH
L1
TP4
TP5
U8
D1
L4
Inductance
1.5 nH
L2
Inductance
10uH
TP1
12 mm Crescent Hook Feasibility and Migration Plan
User constraint
The behind-ear hook must be a smooth, slim moon-crescent that follows and hides behind the ear. Maximum hook width is 12 mm. USB-C should remain at the bottom/tail.
Current layout status
  • Current hook board outline: about 28.23 mm wide × 54 mm tall, custom crescent.
  • Current component envelope: about 24.1 mm wide × 50.28 mm tall.
  • Current stackup reported by layout: 2 copper layers, despite earlier 4-layer intent.
  • Routing analysis reports the current placement as unroutable/congested near U1/U2/U7.
Feasibility conclusion
A 12 mm-wide crescent is not achievable by simply squeezing the current layout. The current component envelope is roughly 2× too wide, and several selected parts consume most of the 12 mm width by themselves. The product needs a tighter two-board/flex architecture and smaller packages.
Parts driving width
  • J1 current USB-C footprint: about 9.64 × 8.08 mm. This can fit within 12 mm only at the lower tail and should use a mid-mount/low-profile replacement.
  • U7 W25Q01JVZEIQ flash footprint: about 9.25 × 6.6 mm. This is too large for the crescent body and should be replaced with a WSON/USON or smaller flash option, or moved/removed if not needed for prototype.
  • MIC1/MIC2 current ICS-40730 footprints: about 4–6 mm body envelope each. Replacement should be smaller, active lifecycle, and high SPL.
  • SW1 tactile switch: about 5.59 × 3.08 mm. Consider deleting from the wearable hook or replacing with magnetic/Hall/button-on-flex/user-app control.
  • J3/J2 connectors: 6–7.7 mm footprints. Flex/battery interconnect choices must be chosen around 12 mm max width.
Microphone sourcing result
Current ICS-40730 is not preferred for new design. Good active high-SPL analog differential mic candidates found on web:
  • TDK InvenSense ICS-40638: analog differential, 138 dB SPL AOP, 3.5 × 2.65 × 0.98 mm.
  • Infineon IM70A135: analog differential, 132/135 dB SPL AOP, 70 dBA SNR, 3.5 × 2.65 × 1.0 mm.
  • Infineon IM73A135: analog differential, 132/135 dB SPL AOP, 73 dBA SNR, 4.0 × 3.0 × 1.2 mm. Flux library did not return an exact high-SPL analog differential active mic match with confirmed AOP; the selected mic likely needs part creation/import.
USB-C sourcing result
Flux library candidates:
  • TYPE-C-16M-0243MD: compact SMT mid-mount/hybrid USB-C, Flux library candidate.
  • USB4105-GF-A: GCT active USB-C USB 2.0 receptacle, right-angle SMT/TH retention. Web candidates for smaller mechanical stack:
  • Same Sky UJ20-C-H-G-MSMT-10B-P16-TR: USB 2.0 mid-mount, 1.06 mm profile.
  • Amphenol 12402307E512A: USB 2.0 mid-mount, 0.4 mm center height.
  • Amphenol GSB1C4621DS2HR: USB 2.0 mid-mount, recessed center-height option. Exact mechanical drawing must be checked before replacing J1.
Keep the hook PCB to core compute/control/power only, and push audio power/output hardware into the IEM-side board/flex assembly.
Hook board should contain:
  • nRF5340 or possibly a smaller module/SiP if RF layout risk is too high.
  • nPM1100 or smaller charger/power-path PMIC.
  • CS47L63 only if the 12 mm placement remains feasible; otherwise move codec/DSP closer to the IEM side or use a narrower package/architecture.
  • 2× high-SPL analog differential MEMS mics on the outward edge.
  • Small flash only if required.
  • Low-profile USB-C at lower tail.
  • Battery tabs/connector along the inner crescent or stacked mechanically with enclosure support.
  • 7-conductor flex exit toward IEM.
IEM-side board/flex should contain:
  • 3× MAX98360A amps.
  • BA receivers and acoustic structure.
  • Local decoupling and any required output/filter components.
Layout plan before next mutation
  1. Replace hard feasibility target with a 12 mm max-width smooth crescent outline, likely about 55–65 mm long depending on ear contour.
  2. Switch stackup to 4 layers for routing density and RF integrity.
  3. Replace current bulky USB-C with a compact mid-mount candidate after mechanical verification.
  4. Replace ICS-40730 with ICS-40638 or IM70A135 after part creation/import.
  5. Replace or remove the large WSON8 flash if storage is not essential for first prototype.
  6. Remove/miniaturize the physical button.
  7. Move non-hook components and IEM-side audio power hardware fully out of the hook layout.
  8. Re-place along the crescent as a single-file chain: USB/power at lower tail, battery zone along inner side, nPM1100, nRF5340, CS47L63, RF/antenna at upper tail, mics on outer edge.
Risk
At 12 mm width, the design is mechanically plausible only as a highly optimized wearable PCB with small packages, dense 4-layer routing, and enclosure/battery co-design. A quick prototype board can be wider; the product-like board cannot keep the current generic footprints unchanged.
  • User constraint

  • Current layout status

  • Feasibility conclusion

  • Parts driving width

  • Microphone sourcing result

  • USB-C sourcing result

  • Recommended architecture change for 12 mm width

  • Layout plan before next mutation

  • Risk