Aurora Hearing Device Design

Blocked: your account is currently out of ACUs, so I can’t mutate the board/layout further in this run.
Accomplished this session:
  • Started the 12 mm product-like redesign workflow.
  • Loaded the required layout/component procedures for the crescent board, compact part replacement, and placement constraints.
  • Confirmed the next execution plan: 12 mm max-width smooth crescent, 4-layer stackup, compact USB-C replacement, high-SPL mic replacement, removal/shrinking of bulky hook-side parts, and dense two-sided placement.
Remaining:
  • Apply the new 12 mm crescent board outline and 4-layer stackup.
  • Replace/flag oversized parts: current USB-C, ICS-40730 mics, large flash, tactile switch, and bulky connectors.
  • Re-place the hook PCB components into the slim crescent form factor.
  • Run layout fit/congestion checks and update the project documentation.
Estimate the ACUs needed to finish the 12 mm redesign.
Estimate: ~25–45 ACUs to finish a credible 12 mm hook redesign pass.
Breakdown:
  • Apply 12 mm crescent outline + 4-layer stackup: 2–5 ACUs
  • Research/replace compact USB-C + high-SPL mics + smaller flash/switch/connectors: 6–12 ACUs
  • Re-place dense two-sided hook layout: 8–15 ACUs
  • Fit/congestion/layout verification: 4–8 ACUs
  • Update project docs and next-step notes: 2–5 ACUs
If we also route the board afterward, budget another 40–90 ACUs, because fine-pitch nRF5340/CS47L63, RF, USB, and dense wearable placement will likely need multiple iterations.
Proceed after ACUs
Prioritize fit check
Research compact parts
Update migration plan
Review power impact
Y1
SPK1
U6
J1
ANT1
J2
U5
U4
SPK3
MIC2
End of Life
SPK2
U3
MIC1
End of Life
J1 VBUS - U6 VBUS
U1 P0.22 - U2 ASP2_DIN/GPIO6
U2 VREF1_FILT - C21 P1
U1 VDD_3 - U1 VDD_4
U2 AS[1_DOUT/GPIO1 - U3 DAI2
J1 CC2 - R4 P1
L4 P2 - ANT1 FEEDING_POINT
U1 DECN - C18 P1
U8 EN - C6 P1
U1 VDD_9 - U1 VDDH
U2 VREF1_FILT - C21 P1
U1 DCC - L2 P1
MIC2 OUTPUT+ - C26 P1
U1 P0.24 - U2 IRQ
L4 P2 - ANT1 FEEDING_POINT
U1 VDD_9 - U1 VDDH
U2 VREF2_FILT - C22 P1
U1 NRESET - TP3 P1
U5 OUTN - SPK3 TERMINAL_1
U1 VDD_9 - U1 VDDH
U1 VDD_9 - U1 VDDH
U1 VDD_9 - U1 VDDH
C25 P2 - U2 IN1LN_1
U6 VSYS - U10 VIN
U1 VDD_9 - U1 VDDH
U8 BP - C8 P1
U1 VDD_9 - U1 VDDH
MIC2 OUTPUT+ - C26 P1
C27 P2 - U2 IN2LN
L2 P2 - U1 DECR
J1 D- - U1 D-
U1 P0.25/AIN4 - U3 EN
U6 VSYS - U10 VIN
J1 CC1 - R3 P1
J1 D- - U1 D-
U3 OUTN - SPK1 COIL_A
U5 OUTP - SPK3 TERMINAL_2
U6 NTC - R9 P1
U7 DI_(IO0) - U1 P0.13/IO0
U1 P0.25/AIN4 - U3 EN
U9 OUT - C10 P1
MIC1 OUTPUT- - C25 P1
U6 DEC - C23 P1
U1 P1.03/TWI - U2 SPI1_MOSI/I2C1_SDA
C24 P2 - U2 IN1LP_1
U1 P0.23 - U2 RESET
U1 P1.02/TWI - U2 SPI1_MISO/I2C1_SCL
U1 P0.25/AIN4 - U3 EN
J1 D+ - U1 D+
J3 1 - D1 A
U1 P0.21 - U2 ASP2_FSYNC/GPIO8
U6 VSYS - U10 VIN
U1 VDD_9 - U1 VDDH
U1 ANT - L4 P1
U9 OUT - C10 P1
L3 P2 - U1 DECD
U8 BP - C8 P1
U3 OUTP - SPK1 COIL_B
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U1 P0.23 - U2 RESET
U1 VDD_3 - U1 VDD_4
U9 EN - C9 P1
U7 ~WP_(IO2) - U1 P0.15/IO2
U3 OUTP - SPK1 COIL_B
U10 FB - R1 P2
U1 VDD_3 - U1 VDD_4
U7 ~WP_(IO2) - U1 P0.15/IO2
MIC1 OUTPUT- - C25 P1
U1 XC1 - Y1 XTAL1
U1 DECN - C18 P1
U7 DO_(IO1) - U1 P0.14/IO1
U1 P0.25/AIN4 - U3 EN
U6 VSYS - U10 VIN
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U2 AS[1_DOUT/GPIO1 - U3 DAI2
U1 XC2 - Y1 XTAL2
U1 XC2 - Y1 XTAL2
U7 ~HOLD_OR_~RESET_(IO3) - U1 P0.16/IO3
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U1 SWDIO - TP1 P1
MIC2 OUTPUT- - C27 P1
L4 P2 - ANT1 FEEDING_POINT
U1 P0.25/AIN4 - U3 EN
U1 DECUSB - C20 P1
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U6 VSYS - U10 VIN
U10 SW - L1 1
U7 ~CS - U1 P0.18/CSN
J1 CC2 - R4 P1
J1 VBUS - U6 VBUS
U7 CLK - U1 P0.17/SCK
U1 DECRF - C15 P1
U6 VSYS - U10 VIN
U1 VDD_9 - U1 VDDH
U1 P0.24 - U2 IRQ
U6 VSYS - U10 VIN
U1 P0.11/TRACEDATA0/CSN - SW1 1
U1 VDD_9 - U1 VDDH
J1 D+ - U1 D+
U1 VDD_9 - U1 VDDH
U2 AS[1_DOUT/GPIO1 - U3 DAI2
U3 OUTN - SPK1 COIL_A
C24 P2 - U2 IN1LP_1
U1 DECA - C19 P1
U6 NTC - R9 P1
U1 XC2 - Y1 XTAL2
U6 VSYS - U10 VIN
U6 DEC - C23 P1
C26 P2 - U2 IN2LP
U1 VDD_9 - U1 VDDH
U1 P1.02/TWI - U2 SPI1_MISO/I2C1_SCL
J3 1 - D1 A
U1 XC1 - Y1 XTAL1
U9 EN - C9 P1
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U1 P1.03/TWI - U2 SPI1_MOSI/I2C1_SDA
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U1 DCCD - L3 P1
U1 VDD_1 - U1 VDD_2
U1 DCC - L2 P1
L3 P2 - U1 DECD
U5 OUTP - SPK3 TERMINAL_2
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U4 OUTN - SPK2 N
U4 OUTN - SPK2 N
U9 OUT - C10 P1
U1 P0.21 - U2 ASP2_FSYNC/GPIO8
D1 K - U6 VBAT
J1 VBUS - U6 VBUS
U1 P0.25/AIN4 - U3 EN
U1 DECRF - C15 P1
J1 CC1 - R3 P1
U4 OUTP - SPK2 P
U9 OUT - C10 P1
U6 VSYS - U10 VIN
U2 AS[1_DOUT/GPIO1 - U3 DAI2
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U1 DCCD - L3 P1
C27 P2 - U2 IN2LN
U2 VREF2_FILT - C22 P1
U1 P0.11/TRACEDATA0/CSN - SW1 1
J1 D- - U1 D-
U6 ICHG - R8 P1
U1 P1.03/TWI - U2 SPI1_MOSI/I2C1_SDA
MIC1 OUTPUT+ - C24 P1
U1 VDD_9 - U1 VDDH
U1 XC1 - Y1 XTAL1
U10 SW - L1 1
U1 SWDIO - TP1 P1
U5 OUTN - SPK3 TERMINAL_1
U1 ANT - L4 P1
L2 P2 - U1 DECR
MIC1 OUTPUT+ - C24 P1
C25 P2 - U2 IN1LN_1
U2 AS[1_DOUT/GPIO1 - U3 DAI2
U1 DECRF - C15 P1
U1 P0.20 - U2 ASP2_BCLK/GPIO7
U6 VSYS - U10 VIN
MIC2 OUTPUT- - C27 P1
U4 OUTP - SPK2 P
U1 DECA - C19 P1
U1 VDD_9 - U1 VDDH
J1 D+ - U1 D+
U10 FB - R1 P2
U7 DI_(IO0) - U1 P0.13/IO0
U8 OUT - C7 P1
U1 SWDCLK - TP2 P1
C26 P2 - U2 IN2LP
U1 VDD_3 - U1 VDD_4
D1 K - U6 VBAT
U1 P1.02/TWI - U2 SPI1_MISO/I2C1_SCL
U8 EN - C6 P1
U6 ICHG - R8 P1
U6 VSYS - U10 VIN
U1 P0.22 - U2 ASP2_DIN/GPIO6
U1 ANT - L4 P1
U1 VDD_3 - U1 VDD_4
U10 FB - R1 P2
L3 P2 - U1 DECD
U6 VSYS - U10 VIN
U6 VSYS - U10 VIN
U8 EN - C6 P1
U8 OUT - C7 P1
U1 NRESET - TP3 P1
U1 P0.20 - U2 ASP2_BCLK/GPIO7
U8 OUT - C7 P1
U2 ASP1_BCLK/GPIO3N - U3 DAI0
U1 VDD_1 - U1 VDD_2
U7 DO_(IO1) - U1 P0.14/IO1
U7 ~HOLD_OR_~RESET_(IO3) - U1 P0.16/IO3
U1 DECUSB - C20 P1
U1 VDD_9 - U1 VDDH
U10 FB - R1 P2
U1 VDD_9 - U1 VDDH
U7 CLK - U1 P0.17/SCK
U2 ASP1_FSYNC/GPIO4 - U3 DAI1
U6 VSYS - U10 VIN
U1 VDD_3 - U1 VDD_4
U7 ~CS - U1 P0.18/CSN
U1 SWDCLK - TP2 P1
C7 P2 - C8 P2
U6 AVSS_EP - U6 PVSS
C15 P2 - C16 P2
GND
R8 P2 - U6 ISET
U1 VSS_4 - U1 VSS_5
C7 P2 - C8 P2
U10 GND - C2 P2
C15 P2 - C16 P2
U10 GND - C2 P2
R8 P2 - U6 ISET
R8 P2 - U6 ISET
C30 P2 - C31 P2
U6 AVSS_EP - U6 PVSS
U1 AVSS_3 - U2 GND_A
J1 GND - R3 P2
U2 GND_D - U2 GND_SUB
U10 GND - C2 P2
R8 P2 - U6 ISET
Y1 GND - C4 P2
U2 GND_D - U2 GND_SUB
C21 P2 - C22 P2
ANT1 GND_2 - U2 VDD_LDO
C15 P2 - C16 P2
R7 P2 - U3 GAIN_SLOT
U1 AVSS_1 - U1 AVSS_2
R8 P2 - U6 ISET
J1 GND - R3 P2
U1 VSS_12 - U1 VSS_13
C15 P2 - C16 P2
U1 AVSS_3 - U2 GND_A
GND
U6 AVSS_EP - U6 PVSS
U5 GND_2 - J2 GND
R8 P2 - U6 ISET
C28 P2 - C29 P2
U1 AVSS_3 - U2 GND_A
U1 VSS_4 - U1 VSS_5
Y1 GND - C4 P2
U1 VSS_12 - U1 VSS_13
C7 P2 - C8 P2
U2 GND_D - U2 GND_SUB
ANT1 GND_2 - U2 VDD_LDO
R8 P2 - U6 ISET
U6 AVSS_EP - U6 PVSS
GND
U2 GND_D - U2 GND_SUB
C30 P2 - C31 P2
U10 GND - C2 P2
Y1 GND - C4 P2
U6 AVSS_EP - U6 PVSS
C21 P2 - C22 P2
U6 AVSS_EP - U6 PVSS
R8 P2 - U6 ISET
C15 P2 - C16 P2
U2 GND_D - U2 GND_SUB
U1 AVSS_3 - U2 GND_A
U10 GND - C2 P2
C15 P2 - C16 P2
C28 P2 - C29 P2
C21 P2 - C22 P2
GND
U1 AVSS_3 - U2 GND_A
R7 P2 - U3 GAIN_SLOT
U6 AVSS_EP - U6 PVSS
R8 P2 - U6 ISET
U6 AVSS_EP - U6 PVSS
C28 P2 - C29 P2
J1 GND - R3 P2
U10 GND - C2 P2
U5 GND_2 - J2 GND
U2 GND_D - U2 GND_SUB
U1 AVSS_1 - U1 AVSS_2
U10 GND - C2 P2
C31
Capacitance
DNP F
C8
Capacitance
0.01uF
C26
Capacitance
2.2 µF
C24
Capacitance
2.2 µF
C20
Capacitance
100nF
C13
Capacitance
1uF
C3
Capacitance
6.8pF
C9
Capacitance
1uF
C5
Capacitance
12pF
C28
Capacitance
0.1 µF
C21
Capacitance
2.2uF
C27
Capacitance
2.2 µF
C30
Capacitance
DNP F
C22
Capacitance
10uF
C10
Capacitance
1uF
C18
Capacitance
100nF
C12
Capacitance
1uF
C23
Capacitance
10uF
C19
Capacitance
1uF
C14
Capacitance
10uF
C1
Capacitance
4.7uF
C2
Capacitance
10uF
C15
Capacitance
1uF
C25
Capacitance
2.2 µF
C29
Capacitance
0.1 µF
C6
Capacitance
0.1uF
C4
Capacitance
12pF
C16
Capacitance
2.2nF
C7
Capacitance
2.2uF
C17
Capacitance
1uF
C11
Capacitance
1uF
U1
R9
Resistance
10kΩ
SW1
R4
Resistance
5.1kΩ
U2
R6
Resistance
4.7kΩ
R2
Resistance
100kΩ
R3
Resistance
5.1kΩ
R7
Resistance
100kΩ
R5
Resistance
4.7kΩ
R1
Resistance
400kΩ
R8
Resistance
11kΩ
J3
U7
U10
TP2
TP3
U9
TP4
TP5
TP1
L3
Inductance
10uH
L1
U8
D1
L4
Inductance
1.5 nH
L2
Inductance
10uH

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Schematic Wiring Status — Project Aura
Status
Core schematic wiring and the main support-passive pass are complete. A focused electrical/passive review now reports no open warnings for floating pins, no-connects, power pins, single-pin nets, shorted components, undriven nets, decoupling caps, capacitor voltage rating, or pull-up/pull-down checks.
Remaining work is now primarily schematic readability cleanup and PCB/layout-stage validation: RF physical placement/keepout, controlled-impedance routing, VNA antenna tuning, and final audio/power validation before manufacturing.
Major Correction Made During Wiring
The 7-conductor flex interpretation was revised after the analog ICS-40730 hook microphones were added.
Corrected placement assumption:
  • Hook side: nRF5340, nPM1100, TLV62568 3V0 buck, flash, USB-C, battery connector, two ICS-40730 analog microphones, CS47L63, CS47 1V8/1V2 regulators.
  • IEM side: three MAX98360A amplifiers and the three Knowles BA receivers.
Corrected 7-conductor flex signals:
  1. VSYS_AMP
  2. GND
  3. GND_SHIELD
  4. TDM_BCLK
  5. TDM_FSYNC
  6. TDM_DOUT
  7. AMP_EN
This preserves the 7-conductor constraint while avoiding the impossible case of sending two analog differential microphones across the same limited flex.
Wired Blocks
Power / Charging
  • USB-C VBUS, CC1/CC2 sink pull-downs, USB D+/D− to nRF5340 and nPM1100 port-detect pins.
  • JST-PH battery connector through BAT54 prototype Schottky protection to nPM1100 VBAT.
  • nPM1100 VSYS to MAX98360A supply branch and TLV62568 VIN.
  • nPM1100 charger configuration: 11 kΩ ICHG resistor for ~50 mA charge current, ISET low for USB detection/default 100 mA behavior, VTERMSET high for 4.2 V termination, MODE low, SHPHLD/SHPACT low, fixed 10 kΩ NTC resistor for prototype no-thermistor case, and DEC capacitor populated.
  • nPM1100 VOUTB/SW are intentionally unused because the main 3V0 rail is provided by the external TLV62568 buck.
  • TLV62568 3V0 buck: 2.2 uH inductor, 4.7 uF input cap, 10 uF output cap, 400k/100k feedback divider, 6.8 pF feed-forward cap.
  • TPS79318 1V8_A rail for CS47L63 VDD_A.
  • TLV70012 1V2_D rail for CS47L63 VDD_D.
Compute / Storage / USB
  • nRF5340 VDD pins tied to 3V0; grounds tied to GND.
  • nRF5340 Nordic reference DEC/DC-DC support added: DECR/DECRF, DECD, DECN, DECA, and DECUSB networks with reference values.
  • SWDIO, SWDCLK, nRESET, GND, and 3V0 test pads added.
  • W25Q01JV QSPI flash wired to nRF5340 P0.13–P0.18 QSPI pins.
  • USB-C D+/D− wired to nRF5340 USB and nPM1100 USB detection.
  • 32 MHz MP06003 crystal wired to nRF5340 XC1/XC2 with 12 pF load capacitors.
Audio / Control
  • nRF5340 to CS47L63 control: I2C on P1.02/P1.03 with 4.7k pull-ups to 3V0.
  • nRF5340 to CS47L63 stereo audio: I2S BCLK/FSYNC/DOUT to CS47L63 ASP2 input.
  • CS47L63 VREF1_FILT and VREF2_FILT capacitors added per datasheet.
  • CS47L63 VDD_LDO is intentionally unused because the external ICS-40730 MEMS microphones are powered from 3V0; per datasheet, VDD_LDO and LDO_FILT are tied to GND.
  • CS47L63 to MAX98360A amps: ASP1 TDM BCLK/FSYNC/DOUT bus.
  • MAX98360A TDM slot straps: U3 slot 0, U4 slot 1, U5 slot 2 by leaving U5 GAIN_SLOT open.
  • AMP_EN from nRF5340 P0.25 to all MAX98360A EN pins and flex AMP_EN, with 100k pulldown default-off.
  • MAX98360A outputs wired to WBFK, CI, and TWFK BA receiver terminals.
  • ICS-40730 microphones now include local 0.1 uF VDD decoupling and 2.2 uF series DC-blocking capacitors on each differential output before the CS47L63 analog inputs.
RF
  • Replaced the temporary direct nRF5340 ANT-to-antenna feed with a tunable RF matching footprint.
  • Added L4 as the initial 1.5 nH series matching element based on Johanson 2450AT42E010B evaluation-board guidance.
  • Added C30/C31 as optional DNP 0201 C0G/NP0 shunt tuning pads on the nRF side and antenna side of the series element.
  • Marked RF_NRF_2G4 and RF_ANT_2G4 as 50 Ω controlled-impedance high-speed nets.
  • Final component values still require final PCB geometry, antenna placement, and VNA tuning; Johanson notes that client PCB matching values will differ from evaluation-board values.
Latest Focused ERC Result
Focused review types checked:
  • Floating pins
  • No-connect issues
  • Power pins
  • Single-pin nets
  • Pin-to-pin issues
  • Shorted components
  • Undriven nets
  • Decoupling caps
  • Pull-up / pull-down checks
  • Capacitor voltage rating
Result: no open warnings or errors returned for those focused electrical/passive categories as of 2026-07-17.
Remaining Work Before Layout
  1. Clean up schematic readability: many auto-generated portals/wires are visually dense and can trigger schematic collision/readability warnings.
  2. During PCB setup, place the Johanson antenna and L4/C30/C31 matching network exactly per RF layout constraints, with short 50 Ω CPWG feed and appropriate ground/keepout behavior.
  3. VNA-tune the RF matching network on the final board; L4/C30/C31 values are starting/tuning placeholders, not production-final values.
  4. Verify MAX98360A logic thresholds with VSYS supply and 3V0 TDM input signals.
  5. Replace BAT54 Schottky with ideal-diode MOSFET protection if voltage drop/headroom is unacceptable.
  6. Add current-measurement jumpers or explicit test points for VSYS, 3V0, 1V8_A, 1V2_D, and amp supply if measurement priority is high.
  7. Confirm nRF5340 VDDH/DCCH regulator-mode choice against Nordic reference layout before final PCB layout.
Latest Change Note
2026-07-17: Added ICS-40730 microphone AC-coupling and local decoupling, tied unused CS47L63 LDO pins per datasheet, added the RF matching/tuning footprint, marked RF nets as 50 Ω, and re-ran focused electrical/passive ERC clean.
  • Status

  • Major Correction Made During Wiring

  • Wired Blocks

  • Power / Charging

  • Compute / Storage / USB

  • Audio / Control

  • RF

  • Latest Focused ERC Result

  • Remaining Work Before Layout

  • Latest Change Note

Project Aura Hearing Device

Project Aura Hearing Device thumbnail
Left-ear prototype for Project Aura: a BLE hearing-device/IEM concept with nRF5340 compute, rechargeable LiPo power, digital microphones, flash storage, USB-C, and a multi-driver in-ear body. Current status: requirements captured; schematic capture is blocked pending audio/flex architecture correction.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$66.80–$74.29

Digi-Key

$16.60

HQonline

$1.65

LCSC

$82.52

Mouser

$61.56

TME

$0.22

Verical

$19.92–$30.08

Controls