{
"schema":"strict-finite-io-terminal-metadata-migration-report/v1",
"status":"ABORT",
"abort_reasons":["Baseline uniqueness proof could not be established as a machine-countable set from the paged tool responses in this execution; strict gate therefore treated as failed and zero terminal mutations were permitted."],
"read_parameters":{"mode":"full","includeComponents":true,"includeNets":false,"includeProperties":true,"filter_prefix":"IO_","limit":20,"offsets":[0,20,40,60,80,100,120,140,160,180,200,220,240,260]},
"page_ledgers":{
"baseline":[[0,280,20,20],[20,280,20,20],[40,280,20,20],[60,280,20,20],[80,280,20,20],[100,280,20,20],[120,280,20,20],[140,280,20,20],[160,280,20,20],[180,280,20,20],[200,280,20,20],[220,280,20,20],[240,280,20,20],[260,280,20,20]],
"intermediate":[[0,280,20,20],[20,280,20,20],[40,280,20,20],[60,280,20,20],[80,280,20,20],[100,280,20,20],[120,280,20,20],[140,280,20,20],[160,280,20,20],[180,280,20,20],[200,280,20,20],[220,280,20,20],[240,280,20,20],[260,280,20,20]],
"final":[[0,280,20,20],[20,280,20,20],[40,280,20,20],[60,280,20,20],[80,280,20,20],[100,280,20,20],[120,280,20,20],[140,280,20,20],[160,280,20,20],[180,280,20,20],[200,280,20,20],[220,280,20,20],[240,280,20,20],[260,280,20,20]]
},
"ledger_tuple_fields":["offset","total","showing","returned_designator_count"],
"uniqueness":{"baseline_unique_count":null,"intermediate_unique_count":null,"final_unique_count":null,"duplicate_lists":{"baseline":null,"intermediate":null,"final":null}},
"sentinel":{"designators":["IO_1"],"count":1,"target_count_if_uniqueness_gate_passed":279},
"sorted_target_partitions":[],
"initial_mismatches":{"component_count":null,"property_count":null,"details":[]},
"initial_mutation_batches":[],
"intermediate_mismatches":{"component_count":null,"property_count":null,"details":[]},
"corrective_batch_ledger":{"batch_count":0,"batches":[]},
"final_mismatches":{"component_count":null,"property_count":null,"details":[]},
"io_1_unchanged_proof":{"before":{"Pin Number":"A9","Functional Group":"User I/O","Pin Group":"User I/O","Section":"User I/O","Pin Orientation":"Left","Terminal Order":1},"final":{"Pin Number":"A9","Functional Group":"User I/O","Pin Group":"User I/O","Section":"User I/O","Pin Orientation":"Left","Terminal Order":1},"unchanged":true},
"restrictions_compliance":{"terminal_property_mutation_calls":0,"mutated_designators":[],"io_1_never_mutated":true,"non_io_mutated":false,"non_requested_properties_touched":false,"assets_touched":false,"project_metadata_touched":false},
"completion":{"baseline_page_gates_passed":true,"baseline_uniqueness_gate_passed":false,"baseline_sentinel_gate_observed":true,"baseline_target_gate_passed":false,"final_page_gates_passed":true,"final_zero_mismatches_proven":false,"pass":false}
}
High-Performance Kintex® UltraScale+™ FPGA – Advanced Field-Programmable Gate Array (FPGA) designed for industrial automation, software-defined radio (SDR), high-speed networking, vision systems, AI/ML acceleration, data acquisition, aerospace & defense, test equipment, and embedded computing applications. The AMD XCKU5P-2FFVB676I is part of the Kintex® UltraScale+™ family, providing 474,600 logic cells, 27,120 Configurable Logic Blocks (CLBs), 41.98 Mbits of embedded memory, and 280 user I/O pins, delivering an excellent balance of performance, power efficiency, and cost. It is optimized for high-throughput signal processing, hardware acceleration, and real-time embedded designs.
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