How to Choose Decoupling Capacitors with PDN Simulation, Not Rules of Thumb

To choose decoupling capacitors, set a target impedance for each power rail, simulate the impedance of the power distribution network (PDN) with capacitor models that include real ESR and ESL, and check the voltage droop when the load current steps. Then use the smallest set of capacitors that keeps the rail inside its limits.

In Flux, you ask the agent to do this. It reads the datasheets, builds the PDN model, runs the impedance sweep and the load-step simulation, picks the capacitors, and puts them in the schematic, the BOM, and the layout. What took a power integrity specialist days takes the agent a few hours.

The rule of thumb is a guess

Most boards still get their decoupling from a rule that is older than most of the parts on them:

• One 100 nF ceramic capacitor on every power pin.
• One 10 µF bulk capacitor for each rail.
• Copy the reference design, and add a few more capacitors to be safe.

That rule came from 5 V logic with slow edges. A modern SoC, FPGA, or MCU runs its core at 1 V or less, with an allowed ripple of a few tens of millivolts. It pulls amperes in nanoseconds when it wakes up. The rule of thumb does not know any of these numbers.

So it fails in two directions:

• Too few capacitors, or the wrong values. The rail droops when the processor wakes up. You find it at bring-up as random resets, jitter on a clock, or a radio that loses packets. Then you rework the board and spin it again.
• Too many capacitors. You pay for parts and placements that do nothing. They take board area that the enclosure does not give you, and they block the routing around the BGA.

Our guide to decoupling capacitors in PCB design covers the basics of placement. This post is about the next step: how to choose the capacitors from a simulation.

Start from a target impedance

The PDN must keep the rail voltage inside its tolerance while the load current changes. That gives a target impedance:

Z_target = (V_rail × allowed ripple) / ΔI_load

For example, a 1.0 V core rail with ±3% tolerance allows 30 mV. If the core current can step by 2 A, the target is 30 mV / 2 A = 15 mΩ. The PDN impedance must stay below 15 mΩ from low frequency up to the frequency where the package and on-die capacitance take over.

The regulator holds the impedance low at low frequency. Bulk capacitors take over above the bandwidth of the regulator. Ceramic capacitors of smaller values take over above that. The plane pair helps at the top of the band. Every capacitor covers only a part of the band, and the transitions between them are where boards fail.

For more on how the regulator, planes, and capacitors work together, read power distribution network design in PCBs.

Why real ESR and ESL change the answer

An ideal capacitor has an impedance that falls forever as the frequency increases. A real capacitor does not. It has equivalent series resistance (ESR) and equivalent series inductance (ESL):

• Below its self-resonant frequency, the capacitor acts like a capacitor, and its impedance falls with frequency.
• At its self-resonant frequency, the impedance is at its minimum, and only the ESR is left.
• Above its self-resonant frequency, the ESL controls the impedance, and the capacitor acts like an inductor.

When you put two different capacitors in parallel, one of them is inductive while the other is still capacitive. Between their self-resonant frequencies they form a parallel resonance, an anti-resonance peak. Low-ESR ceramic capacitors make that peak sharp and tall. A peak above the target impedance is a frequency where the rail rings when the load switches.

A spreadsheet with ideal capacitors does not show these peaks. A simulation with real capacitor models does. That is why the package size, the dielectric, and the capacitor type matter as much as the capacitance value. It is also why a polymer or tantalum bulk capacitor, with its higher ESR, can damp a peak that three more ceramic capacitors make worse.

How the Flux agent picks the decoupling capacitors

Tell Flux which rails to decouple, or ask it to do the full power integrity review of the board. The agent does the work in your project:

1. It reads the datasheets. It gets the rail voltages, the tolerances, the transient currents, and the recommended decoupling of each IC and regulator in the design.
2. It calculates the target impedance of each rail and the frequency band it must cover.
3. It builds the PDN model. The model includes the output impedance of the regulator, the bulk and ceramic capacitors, the plane capacitance and inductance, and the package of the load.
4. It uses vendor capacitor models. These SPICE models come from the capacitor manufacturer, for example Kemet ceramic, tantalum, and polymer capacitors. They include the real ESR, ESL, and impedance over frequency of each part number.
5. It sweeps the PDN impedance across the band, compares it with the target, and finds every anti-resonance peak above the line.
6. It changes the capacitor set and runs the sweep again. It changes values, counts, package sizes, and capacitor types until the impedance stays under the target with the fewest parts.
7. It simulates a load step. It switches the load current, for example from 100 mA to 2 A in a nanosecond, and measures the droop, the recovery time, and the ringing against the rail tolerance.
8. It updates the design. It adds the capacitors to the schematic with real, orderable part numbers, updates the BOM, and places them next to the power pins they decouple.

On a routed board, the agent also calculates IR drop on the power planes and traces and identifies plane resonance. Then it adjusts the decoupling to match the board you will build.

You get the impedance plot against the target, the droop waveform, the final capacitor list, and the reasons for each choice. You can ask why. “Why a 220 µF polymer capacitor instead of two 47 µF ceramic capacitors?” “What is the droop if I remove C14?” The agent answers from the simulation, not from a rule.

Load-step droop is the check that matches bring-up

The impedance sweep is the design tool. The load-step simulation is the proof. It shows what the rail does at the moment your processor leaves sleep mode, or when a radio starts to transmit, or when a motor driver switches.

The agent reports three numbers for each rail:

• Droop: how far the voltage falls below its nominal value.
• Recovery: how long the rail takes to come back inside its tolerance.
• Ringing: how much the rail overshoots and oscillates after the step.

If the droop is too large, the agent changes the capacitors that control that part of the band and runs both simulations again. You see the failure in a simulation in minutes, not on the bench after the boards come back.

Fewer capacitors, more room for the mechanical design

Decoupling is also a mechanical problem. The enclosure sets the board outline. A shield can or a heat sink sets the height of the parts under it. Every capacitor that the rule of thumb adds takes area that the connectors, the mounting holes, and the routing need.

In Flux, the board and the enclosure are in the same project. The agent knows the keep-outs and the height limits from the mechanical design, and it picks capacitors that fit them. If you move the enclosure wall or add a shield can, the agent checks the decoupling and the fit again in the same project.

Prompts to try

Use prompts like these in a Flux project:

• “Set a target impedance for the 0.9 V and 1.8 V rails of the FPGA from its datasheet, then choose decoupling capacitors that keep the PDN impedance under target from 10 kHz to 100 MHz.”
• “Simulate a 100 mA to 2 A load step on the SoC core rail and report the droop, recovery time, and ringing. Change the capacitors until the droop is less than 25 mV.”
• “Use vendor models with real ESR and ESL, and show me every anti-resonance peak above the target.”
• “Remove every decoupling capacitor that the simulation shows does not help, and update the BOM.”
• “The shield can over U2 leaves 1.0 mm above the board. Choose decoupling capacitors that fit under it and still meet the target impedance.”
• “The enclosure is now 6 mm narrower. Check the board outline, the mounting holes, and the decoupling around the processor, and fix what no longer fits.”

Hours, not days

Without Flux, power integrity on a complex board takes days. Someone collects the vendor models, builds the PDN model in a separate tool, runs sweeps, changes values, and then copies the result back into the schematic and the BOM by hand. Many teams skip it and use the rule of thumb instead.

In Flux, the agent does the full loop in your project in a few hours, with the schematic, the layout, and the enclosure in the same place. You decide the targets and review the result. For more on how to use simulation this way, read simulate circuits with a prompt and why hardware simulation is a scoped approximation. The simulation docs list every analysis that Flux runs.

FAQs

How do I choose decoupling capacitors?

What is target impedance in PDN design?

Why do ESR and ESL matter for decoupling capacitors?

Is 100 nF on every power pin enough?

Can Flux simulate power integrity on my PCB?

Try it

Open a project and ask Flux: “Analyze power integrity on this board and choose the decoupling capacitors from a PDN simulation, not from a rule of thumb.” Start Free Trial.