• Project: Vanover's Tiny Tim Design
• Version lock: Tiny Tim Version 4.0 is locked. No connector, geometry, label, quantity, schematic wiring, visual, placement, or documentation change should be made without explicit user request to unlock or create Version 4.1.
• Board type: COM-HPC Mini type carrier-card PCB layout design.
• Initial board target: 115 mm x 120 mm starting outline.
• Primary optimization goal: reduce card size while preserving connector usability, cable exit clearance, module compatibility, and signal integrity.
• Current status: Draft requirements and visual concept stage. No schematic, real component footprints, or routed PCB layout exists yet.
• Active connector table source: Tiny Tim Vertical Connectors v2.0. The earlier v0.5 connector-table basis is superseded and should not be used for quantities or part numbers.

• Host a COM-HPC Mini type module/carrier-card architecture.
• Provide high-density external I/O similar in connector style to the ARK Just A Jetson reference when possible.
• Keep front-side external connectors vertical/top-entry so cables exit away from the board in the Z direction where practical.
• Keep side-edge connections minimal.
• Support rear/bottom-side internal expansion modules and PCIe cable/FFC connection.
• Eventually produce exportable external design/manufacturing files after schematic, layout, placement, routing, and validation are completed.

Diagram

• COM-HPC Mini type carrier-card basis.
• COM-HPC Mini type uses one 400-pin high-speed carrier connector.
• Version 4.0 selected COM-HPC Mini type carrier connector: Samtec ASP-230336-03, 400-position male carrier plug, 10 mm stack height, column termination.
• Reason for 10 mm stack height: more clearance and cooling.
• Exact footprint import/create, module-side compatibility, pinout, mounting pattern, keepouts, and power requirements are still required before real schematic/layout placement.

• 2x 10GbE RJ45.
• Version 4.0 selected part: Bel / TRP G55-122N-155.
• This replaces the incorrect TE 5555165-1 reference; 5555165-1 is RJ25/6P6C Cat3, not RJ45 10GbE.
• Selected connector is a vertical 1x1 RJ45 MagJack ICM with integrated magnetics, 10GBASE-T, through-hole mount, LEDs, 60 W 4PPoE, and -40°C to +85°C operating temperature.
• PoE design is stopped. Do not add a PoE PD controller or PoE power path unless the user explicitly reopens PoE design.
• Exact Flux library part was not found; footprint import/create is likely required.
• Connector style should match ARK Just A Jetson where possible.

• 1x full-size HDMI Type A, 19 pins.
• Candidate style: standard vertical HDMI Type A receptacle.
• HDMI v2.1 target.

• Ethernet: 2x 10GbE RJ45.
• USB: 3x USB-A, 3x USB-C OTG, 1x Type-C TBT, plus USB2 Host functions on JST-GH.
• Display: 1x full-size HDMI Type A.
• Storage/expansion: rear M.2 M/B-key 2280, rear M.2 E/B-key 2230, rear compact x4 PCIe / USB interface candidate.
• Camera: 3x 22-pin CSI FFC; 4x Fakra GMSL.
• Low-speed: UART, CAN/CAN-FD, I2C, SPI, I2S, GPIO, Audio via grouped JST-GH.
• Power: 1x 5V IN redundant power via CLIK-Mate candidate, 1x BAT IN XT60, 1x BAT OUT XT30, 1x fan PicoBlade.

• Power architecture is not yet specified.
• v2.0 explicitly includes 5V IN redundant power, BAT IN, BAT OUT, and fan connector entries.
• Version 4.0 PoE design work is stopped per user instruction. Do not implement PoE unless explicitly reopened.
• Version 4.0 preliminary power budget is captured in Tiny Tim Version 4.0 Power Budget.
• Budget conclusion: nominal full-system operation is estimated around ~108 W and peak/turbo unrestricted operation around ~225 W; use non-PoE high-current 12 V primary input planning.
• Recommendation: use a dedicated 12 V primary input sized at 12 A minimum for nominal operation, or 25 A class for unrestricted peak/turbo operation. Do not rely on 5 V IN for full-system power unless it is redefined as a very-high-current input.
• Version 4.0 primary 12 V input connector is J_12VIN1 = AMASS XT60PW-M. J_12VIN1:Pos is mapped to 12V_IN; J_12VIN1:Neg is mapped to PGND.
• Current ratings, regulator requirements, power sequencing, standby rails, battery support, and runtime goals are TBD.

Diagram

• Goal is a real PCB layout suitable for external export after design completion.
• Connector selection should prioritize real, sourceable parts matching the v2.0 table and ARK Just A Jetson style where possible.
• Exact datasheets and footprints must be verified before schematic/layout execution, especially for M.2, Type-C TBT, RJ45/magnetics, XT60/XT30, and CLIK-Mate board-mount/mating-side role.
• Board export files can be generated later after schematic, layout, DRC/ERC review, and manufacturing checks.
• Expected outputs later may include Gerber/ODB++/IPC-2581, BOM, pick-and-place, STEP/3D, PDF drawings, and other manufacturer-specific packages.

• Bring-up and firmware details are TBD until pin mapping and actual COM-HPC Mini type module/interface mapping are defined.
• Debug access should remain physically accessible.
• USB debug/OTG and grouped low-speed headers should be labeled clearly on silkscreen.

• Initial board: 115 mm x 120 mm.
• Tiny Tim Version 3.0 size-optimization estimate: 105 mm x 115 mm recommended minimum target; 100 mm x 110 mm aggressive stretch target, pending exact footprint and COM-HPC Mini type keepout verification.
• Primary goal: reduce footprint while keeping connector cable exits usable.
• COM-HPC Mini type area: nominal module class 90 mm x 100 mm basis stated by user; exact carrier mechanical spec still needed.
• Front/top side: external connectors should attach vertically/top-entry with cables going away from the card.
• Side-edge connectors: minimize where possible.
• Rear/bottom side: flat M.2 E/B-key 2230, flat M.2 M/B-key 2280, and compact PCIe / USB interface.
• Top/front connector placement should visually and mechanically follow ARK Just A Jetson style where possible.

• Tiny Tim Version 2.0
• Current State Visuals: Tiny Tim Version 2.0

• Use COM-HPC Mini type wording throughout.
• Use Tiny Tim Vertical Connectors v2.0 as the active component table; eliminate v0.5 as a source for quantities and part numbers.
• Treat the current front and rear concept views as locked Tiny Tim Version 2.0 references. Nothing changes unless the user explicitly requests it.
• Use a 115 mm x 120 mm initial board outline, then optimize smaller.
• Make vertical/top-entry front connectors the default strategy.
• Minimize side-mounted connectors.
• Match ARK Just A Jetson connector type/style where possible.
• Put M.2 E/B-key 2230, M.2 M/B-key 2280, and compact PCIe / USB interface on the rear/bottom side.
• Use an iterative Flux design process: generate, visually inspect, update, repeat, then export externally.

• Version 4.0 locked export package: Tiny Tim Version 4.0 Locked Export Package. This is a documentation/schematic-concept export package, not a manufacturing package.
• Tiny Tim Version 4.0 part-number/footprint verification has started. Detailed results are captured in Tiny Tim Version 4.0 Part Verification Results. First Flux-ready schematic connector block has been added; no concept-image geometry, labels, connector placement, or board dimensions were changed.
• Working implementation baseline is Tiny Tim Version 4.0 at 105 mm x 115 mm, copied from the Version 3.0 size-optimized concept.
• COM-HPC Mini connector search results are captured in COM-HPC Mini Connector Search Results. Version 4.0 selected Samtec ASP-230336-03, 10 mm stack height. This exact part was not found in the Flux library; footprint import/create is likely required.
• The JST-GH BM04B/BM06B/BM07B family and Molex 505110-1692 were found in Flux library search or public search results.
• Molex 502578-0600 is the CLIK-Mate 6-position plug housing; Version 4.0 board-side candidate is Molex 5031590600.
• Version 4.0 approved M.2 replacements: TE Connectivity 2199230-4 for rear M.2 E/B-key 2230 and Amphenol MDT420M01501 for rear M.2 M/B-key 2280. Do not use Molex 105450-0401 / 105450-0101 for M.2 footprints.
• Version 4.0 approved 10GbE RJ45 replacement: Bel / TRP G55-122N-155. Do not use TE 5555165-1 for 10GbE; it is RJ25/6P6C Cat3, not RJ45 10GBASE-T.
• Version 4.0 PoE design is stopped. Historical PoE analysis is retained in Tiny Tim Version 4.0 PoE Solution, marked discontinued / do not implement.
• Version 4.0 preliminary power budget is captured in Tiny Tim Version 4.0 Power Budget. It estimates ~108 W nominal full-system load and ~225 W peak/turbo unrestricted load.
• Version 4.0 selected Molex 2047110001 as the Type-C TBT/USB4 connector candidate, replacing the unverified Molex 105450-0201 entry. TBT/USB4 architecture still requires definition beyond connector choice.
• Version 4.0 selected XT60PW-M30.G.Y.T / XT60PW-M30 for BAT IN; exact footprint import/verification is still needed.
• Version 4.0 selected 1x Molex 505110-1692 for the rear PCIe/USB FFC path.
• Version 4.0 selected reasonable candidates for remaining connector gaps: Molex 5031590600, Molex 0525592253, TE 2438987-1, Adam Tech USB-C31-S-VT-CS4-BK-PP-T/R, Molex 0476591100, Molex 2047110001, TE 7-2287906-0, and XT60PW-M30.G.Y.T.
• Version 4.0 BOM candidates and connector verification review are captured in Tiny Tim Version 4.0 BOM Candidates and Connector Verification Review. The live schematic/BOM remains empty until selected connectors are added/imported as real components.
• Live BOM after first connector-block and connector-side USB/PCIe mapping: 11 unique physical parts / 24 connector instances. Schematic has 34 nets after USB-C and rear PCIe FFC connector-side labels. PCB layout is not yet created.
• Connector checks currently show 271 expected floating-pin warnings because COM-HPC Mini source connector, M.2 pin mapping, JST-GH headers, GMSL, CC/SBU, and other subsystem pins are not complete yet.
• Initial connector pin mapping is captured in Tiny Tim Version 4.0 Connector Pin Mapping. USB-C connector-side nets and rear PCIe FFC connector-side nets are now labeled with controlled-impedance metadata; M.2 lane allocation is documented as provisional but not physically wired yet.
• COM-HPC Mini type connector selected: Samtec ASP-230336-03, 10 mm stack height, pending footprint import/create and exact module mechanical requirements.
• COM-HPC connector import/create is currently blocked: exact Samtec ASP-230336-03 is not in Flux library, and no importable EDA library package has been provided. Public PDF/PADS resources are not sufficient for automated import in this session.
• Exact COM-HPC Mini type pinout and mechanical keepouts still need to be sourced before schematic/layout execution.
• Signal-integrity stackup, differential-pair constraints, power budget, and placement/routing rules are not yet defined.

• Created initial project specification from uploaded PDF, PPTX extraction, and user-provided guidelines.
• Locked Tiny Tim Version 1.0 front/rear concept views as the current visual baseline.
• Replaced the v0.5 connector-table basis with Tiny Tim Vertical Connectors v2.0.
• Updated rear M.2 M-key requirement to 2280 per v2.0 / locked rear concept.
• Added exact extracted v2.0 quantities and candidate part numbers.
• Regenerated Version 2.0 front/rear concept visuals using vertical receptacle / top-entry geometry from the v2.0 connector table.
• Locked Tiny Tim Version 2.0: no further connector, geometry, label, quantity, visual, or documentation changes without explicit user request.
• Added verification warnings for part numbers that require datasheet confirmation before real footprint placement.
• Updated Tiny Tim Version 4.0 M.2 connector selections: TE Connectivity 2199230-4 for rear M.2 E/B-key 2230 and Amphenol MDT420M01501 for rear M.2 M/B-key 2280.
• Updated Tiny Tim Version 4.0 COM-HPC Mini type carrier connector selection: Samtec ASP-230336-03, 10 mm stack height, selected for more clearance and cooling.
• Updated Tiny Tim Version 4.0 10GbE RJ45 connector selection: Bel / TRP G55-122N-155, replacing incorrect TE 5555165-1 reference.
• Added Tiny Tim Version 4.0 preliminary power budget and power-architecture recommendation: high-current 12 V primary input for full operation.
• Stopped all PoE design work per user instruction; PoE is historical only and not to be implemented unless explicitly reopened.
• Added Version 4.0 reasonable connector selections for remaining verification gaps, with missing-library/import flags where needed.
• Added Version 4.0 BOM candidate and connector verification review file, including Flux-ready parts, selected parts needing import/create, and open architecture caveats.
• Created first schematic connector block using all Flux-ready selected connector parts and updated live BOM status.
• Added J_12VIN1 AMASS XT60PW-M as the primary non-PoE 12 V input and started schematic pin mapping with 12V_IN and PGND nets.