COM-HPC Carrier Layout
Thought for 15 sec
I’ll update Version 5.0 front-view visuals only so the Compute Module is drawn with correct 90 mm × 100 mm proportions and occupies the appropriate larger area. Version 4.0 stays locked.
Worked for 3 mins 46 sec
Thought for 26 sec
Created image.
You can move the component labels off to the side of the PCB
Worked for 4 mins 54 sec
Redone for Tiny Tim Version 5.0 front view.
Changes applied:
- Compute Module is shown much larger with intended 90 mm × 100 mm proportions.
- Carrier board remains 105 mm × 115 mm.
- Labels moved off the PCB as side callouts to reduce clutter.
- Version 4.0 remains locked and unchanged.
Updated file:
Updated Front View
Image
Redo rear and review
Lock Version 5.0
Compare front views
Check label accuracy
Improve compute module fit
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Tiny Tim Version 4.0 Connector Pin Mapping
Lock Notice
Tiny Tim Version 4.0 is locked. This connector pin-mapping state is frozen as part of Tiny Tim Version 4.0 Locked Export Package.
Scope
This is the first connector pin-mapping matrix for Tiny Tim Version 4.0.
Status: provisional connector-side mapping started.
COM-HPC Connector Import Status
Attempted implementation of Samtec ASP-230336-03 is currently blocked: the exact 400-position connector is not available in the Flux library, and no importable EDA library file has been provided. Public Samtec PDF/PADS resources are useful evidence for footprint creation, but the current import path needs KiCad
.kicad_sym + .kicad_mod, Altium .SchLib + .PcbLib, Eagle .lbr, EasyEDA JSON, or ZIP.Because the real COM-HPC connector symbol is not present, the provisional USB/PCIe/M.2 nets cannot be connected to COM-HPC pins yet without creating fake placeholder pins. Placeholder pins are intentionally avoided.
COM-HPC Mini connector is not yet present in the schematic. The mappings below create connector-side net labels and controlled-impedance intent for USB-C and rear PCIe FFC, but they are not yet connected to COM-HPC Mini pins.
COM-HPC Mini Lane Assumptions — Provisional
These assumptions are used to organize connector-side mapping only. They must be verified against the exact COM-HPC Mini module pinout / PICMG carrier design guide before the COM-HPC connector is wired.
Table
| Assumed COM-HPC Resource | Destination | Rationale / Notes |
|---|---|---|
| PCIe x4 group A | Rear M.2 M/B-key 2280 | NVMe storage should get the highest bandwidth x4 PCIe group. |
| PCIe x1 group B | Rear M.2 E/B-key 2230 | Typical wireless E-key uses PCIe x1 plus USB 2.0. |
| PCIe x1 group C | Rear 16-pin PCIe FFC | Raspberry Pi-style PCIe FFC is x1. |
| USB 2.0 ports | USB-C OTG connectors and M.2 E-key | USB-C connector-side labels created; source allocation TBD. |
| USB 3.x ports | USB-C OTG connectors | One SuperSpeed orientation set is labeled per connector; USB-C mux/role architecture TBD. |
| USB4/TBT | Dedicated Type-C TBT connector candidate | Connector selected as Molex 2047110001, but controller/retimer/lane plan TBD. |
| 10GbE | 2x Bel G55-122N-155 MagJack candidates | PHY location and exact COM-HPC Ethernet interface TBD. PoE stopped. |
Live Schematic Nets Created
Table
| Net | Connected Pins | Purpose |
|---|---|---|
12V_IN | J_12VIN1:Pos | Primary non-PoE 12 V input positive rail. |
PGND | J_12VIN1:Neg, USB-C GND/shield pins, PCIe FFC GND/shield pins | Primary power/signal ground return. |
12 V Input Connector Policy
Version 4.0 primary power input policy:
- Use a non-PoE 12 V primary input.
- Nominal design target: 12 V / 12 A minimum.
- Peak/unrestricted target: 25 A class.
- Selected live schematic connector: J_12VIN1 = AMASS XT60PW-M.
- Existing CLIK-Mate power row is demoted to low-current/service/auxiliary candidate unless the power policy is changed.
Connector-Side USB-C Mapping
Applies to
J_USBC1, J_USBC2, J_USBC3.Power / Ground
Table
| Connector | Pins | Net | Status |
|---|---|---|---|
| J_USBC1 | VBUS_1, VBUS_2, VBUS_3, VBUS_4 | USB_C1_VBUS_5V | Created |
| J_USBC2 | VBUS_1, VBUS_2, VBUS_3, VBUS_4 | USB_C2_VBUS_5V | Created |
| J_USBC3 | VBUS_1, VBUS_2, VBUS_3, VBUS_4 | USB_C3_VBUS_5V | Created |
| J_USBC1..3 | GND_1..GND_8, MH_1, MH_2 | PGND | Created |
USB 2.0
Table
| Connector | Pins | Net | Impedance |
|---|---|---|---|
| J_USBC1 | DP1, DP2 | USB2_C1_DP | 90 Ω differential pair USB2_C1 |
| J_USBC1 | DN1, DN2 | USB2_C1_DN | 90 Ω differential pair USB2_C1 |
| J_USBC2 | DP1, DP2 | USB2_C2_DP | 90 Ω differential pair USB2_C2 |
| J_USBC2 | DN1, DN2 | USB2_C2_DN | 90 Ω differential pair USB2_C2 |
| J_USBC3 | DP1, DP2 | USB2_C3_DP | 90 Ω differential pair USB2_C3 |
| J_USBC3 | DN1, DN2 | USB2_C3_DN | 90 Ω differential pair USB2_C3 |
USB 3.x SuperSpeed — First Orientation Set
Table
| Connector | Pins | Net | Impedance |
|---|---|---|---|
| J_USBC1 | SSTXP1 / SSTXN1 | USB3_C1_TX1_P/N | 85 Ω differential pair USB3_C1_TX1 |
| J_USBC1 | SSRXP1 / SSRXN1 | USB3_C1_RX1_P/N | 85 Ω differential pair USB3_C1_RX1 |
| J_USBC2 | SSTXP1 / SSTXN1 | USB3_C2_TX1_P/N | 85 Ω differential pair USB3_C2_TX1 |
| J_USBC2 | SSRXP1 / SSRXN1 | USB3_C2_RX1_P/N | 85 Ω differential pair USB3_C2_RX1 |
| J_USBC3 | SSTXP1 / SSTXN1 | USB3_C3_TX1_P/N | 85 Ω differential pair USB3_C3_TX1 |
| J_USBC3 | SSRXP1 / SSRXN1 | USB3_C3_RX1_P/N | 85 Ω differential pair USB3_C3_RX1 |
USB-C Pins intentionally not mapped yet
CC1,CC2: require USB-C role/CC controller decision.SBU1,SBU2: require alternate-mode/debug decision.SSTXP2/SSTXN2andSSRXP2/SSRXN2: require USB-C mux/receptacle orientation strategy. They are not connected yet to avoid false architecture assumptions.
Rear PCIe FFC Mapping
Based on Raspberry Pi 5-style 16-pin PCIe FFC pinout for Molex 505110-1692 style connector.
Table
| Pin | Net | Status |
|---|---|---|
| 1, 2 | PCIE_FFC_5V | Created |
| 3 | PCIE_FFC_REFCLK_P | Created, 85 Ω pair PCIE_FFC_REFCLK |
| 4 | PGND | Created |
| 5 | PCIE_FFC_REFCLK_N | Created, 85 Ω pair PCIE_FFC_REFCLK |
| 6 | PGND | Created |
| 7 | PCIE_FFC_RX_P | Created, 85 Ω pair PCIE_FFC_RX |
| 8 | PCIE_FFC_RX_N | Created, 85 Ω pair PCIE_FFC_RX |
| 9 | PGND | Created |
| 10 | PCIE_FFC_TX_P | Created, 85 Ω pair PCIE_FFC_TX |
| 11 | PCIE_FFC_TX_N | Created, 85 Ω pair PCIE_FFC_TX |
| 12 | PGND | Created |
| 13 | PCIE_FFC_PWR_EN | Created |
| 14 | PCIE_FFC_DET_WAKE | Created |
| 15 | PCIE_FFC_CLKREQ_N | Created |
| 16 | PCIE_FFC_RST_B | Created |
| P1, P2 | PGND | Created as shield/mechanical ground |
M.2 Mapping — Provisional, not wired yet
M.2 connector net labels are intentionally not applied yet because:
- The COM-HPC Mini source connector is not in the schematic.
- The M.2 library symbols use generic signal labels and direction naming must be checked against host/module perspective.
- M.2 pinouts include PET/PER direction names that can appear swapped depending on whether the table is written from host or module perspective.
M.2 M/B-key 2280 assumption
- Destination:
J_M2M1. - Function: NVMe storage.
- Lane plan: PCIe x4.
- Power: 3.3 V M.2 rail, current limit TBD.
- Sideband: PERST#, CLKREQ#, PEWAKE#, SMBus/I2C if required.
- Status: lane assumption documented, physical pins not wired.
M.2 E/B-key 2230 assumption
- Destination:
J_M2E1. - Function: wireless / SDR / I/O module.
- Lane plan: PCIe x1 + USB 2.0, optional I2S/PCM depending module.
- Power: 3.3 V M.2 rail, current limit TBD.
- Status: lane assumption documented, physical pins not wired.
JST-GH Auxiliary Headers
The JST-GH Flux symbols include extra terminals beyond connector positions, likely mechanical/shield/mount pins. Functional signal mapping must use connector-position pins only after symbol/footprint review.
Table
| Connector Group | Qty | Intended Function | Mapping Status |
|---|---|---|---|
| J_GH4_1..J_GH4_5 | 5 | USB2 Host / CAN / CAN-FD auxiliary | Planned; pinout TBD |
| J_GH6_1..J_GH6_3 | 3 | UART/GPIO/I2C auxiliary | Planned; pinout TBD |
| J_GH7_1..J_GH7_3 | 3 | SPI/I2S/Audio auxiliary | Planned; pinout TBD |
GMSL / FAKRA
Table
| Connector | Function | Mapping Status |
|---|---|---|
| J_GMSL1..J_GMSL4 | GMSL coax / camera | Coax center/shield mapping TBD; geometry caveat: selected TE 7-2287906-0 is right-angle/edge-mount, not top-entry |
Do Not Connect Yet
Do not wire the following until the exact source/sink architecture is defined:
- USB-C CC pins.
- USB-C SBU pins.
- USB-C second orientation SuperSpeed pins.
- TBT/USB4 connector pins.
- M.2 pins.
- COM-HPC Mini pins.
- GMSL coax pins.
- JST-GH auxiliary headers.
Next Mapping Step
- Obtain exact COM-HPC Mini module pinout / carrier design guide / module vendor lane map.
- Add/import the selected COM-HPC Mini connector, then connect provisional nets to actual COM-HPC pins.
- Decide USB-C controller/CC/mux architecture before mapping CC/SBU/second-orientation SuperSpeed pins.
- Decide external port power caps for USB-A, USB-C, TBT, CSI, GMSL, and JST-GH.
- Confirm fan connector pin order.
- Confirm whether GMSL connectors are direct coax pass-through, serializer/deserializer outputs, or module-provided camera links.
- Then wire one subsystem at a time and rerun ERC after each block.
Lock Notice
Scope
COM-HPC Connector Import Status
COM-HPC Mini Lane Assumptions — Provisional
Live Schematic Nets Created
12 V Input Connector Policy
Connector-Side USB-C Mapping
Power / Ground
USB 2.0
USB 3.x SuperSpeed — First Orientation Set
USB-C Pins intentionally not mapped yet
Rear PCIe FFC Mapping
M.2 Mapping — Provisional, not wired yet
M.2 M/B-key 2280 assumption
M.2 E/B-key 2230 assumption
JST-GH Auxiliary Headers
GMSL / FAKRA
Do Not Connect Yet
Next Mapping Step
