Manufacturing Design Checklist
bruh you didn't even wire it together and created more issues
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Worked for 1 min 3 sec
You’re right. I checked history: the bad work is exactly 8 routing commits from my last pass, and they can be cleanly reverted without touching your earlier manual move or the C1/property fixes.
Safe recovery point:
- Revert to commit #bd42c4c0
- This removes only the 8 bad
mutate_layout_routeedits. - It preserves your prior layout changes and the C1 footprint/property work.
I will not do anything else unless you approve. If you want me to undo the damage, say:
Revert to #bd42c4c0
Revert bad routes
Show route diff
Revert and run DRC
Protect current state
Manual routing plan
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PCB Pre-Layout Gate — Power Stage
Status
Power-first PCB placement is not yet release-ready, but the previous AG59824-LPB pad-footprint blocker has been partially remediated from public Silvertel land-pattern data. The AG59824-LPB layout instance now uses the datasheet-derived 5.00mm x 1.83mm SMD pads, 26.57mm row spacing, 45.31mm group spacing, and 51.6mm x 31.0mm package size. A proper reusable part footprint/STEP association is still preferred before manufacturing release.
Footprint / Land Pattern Verification
Table
| Part / Block | Current status | Evidence / issue | Action before routing |
|---|---|---|---|
| LT4321IUF#PBF U4 | Acceptable footprint family | Datasheet: 16-QFN 4mm x 4mm, 0.65mm pitch, exposed OUTN pad. Current layout footprint uses 16 QFN-style pads plus exposed OUTN pad and matches expected package class. | Verify pin-1 orientation during placement; keep OUTP/OUTN bypass C36 close. |
| BSC040N10NS5ATMA1 Q2-Q9 | Acceptable footprint family | Datasheet: PG-TDSON-8 / SuperSO8, source pins 1-3, gate pin 4, drain pins 5-8 plus exposed drain pad. Current footprint has source, gate, drain fingers and exposed drain pad style. | Use large copper on drain/source pads and thermal vias/planes; use direct-connect for power copper. |
| DMT6008LFG Q1/Q10 | Acceptable footprint family | PowerDI3333-8 library footprint available and already used in schematic. | Add copper pour/thermal spreading for Q1 load switch and Q10 ideal-diode path. |
| LTC4359CDCB U5 | Acceptable footprint family with caveat | Datasheet: 6-DFN 2mm x 3mm. Exposed pad optional VSS; datasheet warns DFN pin spacing may be a concern above 30V and suggests leaving exposed pad open if creepage is a concern. Current schematic connects EP to ISO_GND. | Before release, review creepage/clearance for 24V field conditions; consider EP-open variant if contamination/clearance risk dominates. |
| AG59824-LPB PS1 | Partially remediated; still needs release verification | Datasheet package is about 51.6mm x 31.0mm max; land pattern pad span is about 45.31mm x 26.57mm with 5.00mm x 1.83mm pads. The generated pad geometry was corrected in the PCB instance from Figure 17 dimensions. The official Silvertel Ag59800 STEP ZIP was added as a project asset. | Before manufacturing release, verify pin-1 orientation against the Silvertel drawing and replace the instance-level fix with a proper reusable AG59824-LPB footprint/STEP asset if possible. |
| J2 691241710004 terminal block | Electrically suitable | Datasheet: 5.00mm pitch, 4 positions, 14A rating, 300VAC UL / 250VAC VDE, 30–14AWG. | Good for 3A rail; keep at board edge and provide strain/clearance. |
Installer-Abuse Case Decision
For the current schematic, output protection is designed primarily for:
- Reversed passive load wiring at the 24V output terminal.
- Reverse current/backfeed blocking into the board from the output side.
It is not yet fully validated as a complete industrial eFuse/hot-swap solution for every abuse case, especially:
- an external powered 24V supply connected backwards,
- shorted output cable at full PoE power,
- hot-plug into large downstream capacitance,
- inductive load energy without a defined clamp path.
If those are expected installer conditions, add a dedicated eFuse/hot-swap/load-switch protection stage or expand the LTC4359 protection network per datasheet Figure 14.
3A Copper / Thermal Constraints Applied
The following layout net rules were applied:
Table
| Net | Rule applied |
|---|---|
| ISO_24V | minTraceWidth = 2.0mm |
| 24V_FUSED | minTraceWidth = 2.0mm |
| 24V_OUT | minTraceWidth = 2.0mm |
| LED_SW_RETURN | minTraceWidth = 2.0mm |
| POE_VIN_POS | minTraceWidth = 1.0mm |
| POE_VIN_NEG | minTraceWidth = 1.0mm |
| 3V3 | minTraceWidth = 0.5mm |
Additional layout setup completed:
- 4-layer board stackup retained.
- Mid-Layer 1 assigned as Ground Plane.
- Mid-Layer 2 assigned as Power Plane.
- Ethernet TX/RX nets tagged as 100 ohm differential controlled-impedance pairs.
These are conservative pre-routing minimums. Preferred production routing is copper pours/planes for 24V and return paths, not long narrow traces.
Thermal / Placement Requirements Before Power-First Layout
- Use 4-layer board stackup with a solid ground reference plane and power copper plane/regions.
- Place RJ45, LT4321 active bridge, input TVS, and AG59824-LPB close together, with PoE high-voltage/current paths short and wide.
- Place AG59824-LPB so its thermal-interface region can couple to copper and, ideally, enclosure/gap pad.
- Place 24V output terminal J2 at board edge.
- Place F1, Q10/U5, D3 TVS, and J2 as a tight protected-output chain.
- Place U1 buck and its VIN/SW loop parts away from Ethernet magnetics and MCU crystal areas.
- Use thermal via arrays under/near SuperSO8/PowerDI drain/source copper regions where heat must spread to inner/bottom planes.
Current Decision Gates Before Continuing to Schematic Changes
- CLOSED for rev 1: DALI is a protected-terminal placeholder only. Reserve MCU pins and bring DALI+ / DALI- to the terminal block; do not add the full DALI interface circuit on rev 1.
- CLOSED for rev 1: output protection target is reversed passive load protection only. Externally powered reverse polarity, shorted cable, hot-plug capacitance, and inductive kick are documented rev-2/production concerns.
- CLOSED: do not proceed to placement using only the corrected instance-level AG59824 pad geometry. Stop until AG59824-LPB has a correct reusable footprint/STEP association.
Rev-1 Scope Decisions From User Note
- DALI: placeholder/protected terminal only for this revision.
- 24V output abuse: reversed passive load protection only for first prototype.
- AG59824-LPB footprint: must be correct before placement because it is the critical/expensive power module.
Status
Footprint / Land Pattern Verification
Installer-Abuse Case Decision
3A Copper / Thermal Constraints Applied
Thermal / Placement Requirements Before Power-First Layout
Current Decision Gates Before Continuing to Schematic Changes
Rev-1 Scope Decisions From User Note
