Manufacturing Design Checklist

flux

I had to stop because the account has no available ACUs, so AI tool execution is unavailable right now.
What I completed this session:
  • Ran routing pre-check; broad autoroute is not safe yet due to blocked pins and track-width warnings.
  • Routed several targeted power paths:
    • PS1 +VDC → C1 P1 on ISO_24V
    • C1 P1 → F1 P1 on ISO_24V
    • F1 P2 → Q10 source on 24V_FUSED
    • Q10 drain → J2 pin 1 on 24V_OUT
    • Q1 source → C1 P2 on ISO_GND
    • F1 P2 → U5 IN
    • C1 P1 → U1 VIN
    • U1 VIN → U1 EN
Open items:
  • I could not run the final post-route DRC due to ACUs running out.
  • These routes failed and still need attention:
    • J2 pin 2 → Q1 drain LED switched return
    • U5 OUT → Q10 drain
    • Q10 gate → U5 GATE
Suggested next steps:
  1. Add ACUs, then run one DRC check.
  2. Manually inspect Q1/Q10/U5 local placement and copper clearance.
  3. Route the three failed local connections surgically before any broader routing.
E

ep10292

bruh you didn't even wire it together and created more issues

Screenshot 2026-07-04 at 4.41.38 PM

flux

You’re right. I checked history: the bad work is exactly 8 routing commits from my last pass, and they can be cleanly reverted without touching your earlier manual move or the C1/property fixes.
Safe recovery point:
  • Revert to commit #bd42c4c0
  • This removes only the 8 bad mutate_layout_route edits.
  • It preserves your prior layout changes and the C1 footprint/property work.
I will not do anything else unless you approve. If you want me to undo the damage, say:
Revert to #bd42c4c0
Revert bad routes
Show route diff
Revert and run DRC
Protect current state
Manual routing plan
Sign up to send

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Schematic

Layout

3D View

Project Specification
Prototype / Market Context Update — 2026-07-04
User provided prototype context for the PoE lighting controller:
  • Existing working prototype uses a ZhiPu 95W IEEE 802.3bt splitter as the PoE PD front end, producing a regulated 24V rail into a Philips Hue Perifo track lighting system while bypassing the OEM AC driver.
  • An Olimex ESP32-PoE-ISO board currently handles wired Ethernet control through the splitter passthrough and switches the 24V rail through a relay chain.
  • Measured full prototype load is 72.21W sustained from a UniFi USW Pro XG 48 PoE switch, powering four cylinder spotlights plus two gradient light bars, with stable PoE+++ negotiation and nominal splitter thermal performance.
  • The custom Flux PCB is intended to integrate the Silvertel AG59824 PoE PD front end, 24V rail output, LMR33630 24V-to-3.3V logic buck, STM32G473 MCU, W5500 Ethernet, MOSFET PWM output, and DALI interface.
  • Physical product intent: fixture-location module with RJ45 input and 4-conductor rail output terminal block — Cat6 in, lighting rail out, no additional power/data wiring.
  • Target applications: small medical offices, restaurants, and retail spaces where low-voltage Cat6 retrofit, centralized PoE backup power, per-fixture sensing, lux compensation, and wired network control are strong differentiators.
Project Overview
Status: Draft.
This project is an integrated PoE lighting-control PCB. It accepts Ethernet/PoE input, derives an isolated 24V lighting rail plus a 3.3V logic rail, controls lighting by MOSFET PWM dimming, and exposes DALI plus sensor inputs for lux, occupancy, and temperature/thermal monitoring.
Intended Use
  • Prototype-to-production lighting rail controller for Ethernet-powered lighting installations.
  • Intended to replace relay-style switching with solid-state PWM-capable dimming.
  • Ethernet-only control; no WiFi/BLE antenna assumed.
  • Product may be wired by installers, so output/field-wiring protection is required.
What the Device Should Do
  • Negotiate PoE power from an Ethernet switch/injector.
  • Generate a 24V output rail for lighting/rail power.
  • Generate a regulated 3.3V rail for control electronics.
  • Switch/dim the 24V lighting output with a MOSFET.
  • Communicate over wired Ethernet.
  • Support DALI two-wire lighting control.
  • Read a lux sensor over I2C and occupancy via GPIO/PIR input.
  • Provide development/debug access.
Main Features
  • Integrated isolated PoE PD module for first revision.
  • 24V rail output terminals sized around measured load plus headroom.
  • 3.3V control rail.
  • MCU + W5500 Ethernet controller architecture preferred for production.
  • PWM MOSFET output stage.
  • DALI interface.
  • I2C sensor header and PIR input.
  • Programming/debug header and test points.
  • Reverse-polarity/output miswire protection on field terminals where practical.
System Architecture
Diagram



  
    
  
  
    
  





























RJ45 PoE Ethernet
Integrated isolated PoE PD module
24V Lighting Rail
24V to 3.3V Buck
3.3V Logic Rail
STM32-class MCU
W5500 Ethernet Controller
PWM MOSFET Dimmer
Output Protection
Rail Output Terminals
DALI Interface
I2C Lux Sensor Header
PIR GPIO Input
Hardware Subsystems
  • Power: integrated PoE PD module, isolated 24V conversion, 24V-to-3.3V regulator, protection, bulk capacitance, and test points.
  • Compute/control: STM32-class MCU with GPIO for SPI Ethernet, PWM, DALI control, I2C, PIR, reset, and debug.
  • Ethernet: W5500 Ethernet controller and RJ45 with magnetics.
  • Lighting output: MOSFET dimming path sized for the expected lighting current and thermal margin.
  • DALI: DALI bus interface connected to the rail conductors or dedicated output pins as finalized.
  • Sensors: I2C lux sensor header, PIR input header, optional temperature monitoring.
Interfaces and Connections
  • PoE/Ethernet input: RJ45.
  • Lighting rail output: 24V+, 24V-, DALI+, DALI- terminal block.
  • Sensor input: 3.3V I2C header for lux sensor.
  • PIR input: power, ground, and GPIO signal header.
  • Debug: SWD/programming header.
Power and Runtime Expectations
  • Input source: PoE switch or injector.
  • Output rail target: 24V lighting rail.
  • Logic rail target: 3.3V.
  • Runtime: continuous powered operation; no battery.
Power Tree and Power Budget
Sizing inputs:
  • Measured 24V system draw: 22.90W, about 0.95A at 24V.
  • User-selected design target: 24V output rail with 2–3A production headroom.
  • Practical 24V power target: true 3A headroom at 24V, which requires an 89W-class 802.3bt module or equivalent rather than a 60W-only module.
  • The existing Ag5324 module is now considered prototype-only/undersized for this target.
  • Leading production-headroom candidate: Silvertel AG59824-LPB, IEEE 802.3bt Class 8, 24V 89W-class isolated output.
  • Lower-power fallback candidate: Silvertel Ag5810, IEEE 802.3bt Type 4 Class 7, 60W, configurable 12V/24V isolated output, suitable only if the rail is capped around 2.5A.
  • 3.3V electronics: provisional 250–500mA peak budget.
Power tree:
Diagram



  
    
  
  
    
  




















PoE PSE / Injector
RJ45 + Magnetics
Integrated Isolated PoE PD Module
24V Rail
Lighting Output / MOSFET Dimming
3.3V Buck Regulator
3.3V Logic Rail
MCU
W5500
Sensors and DALI Logic
Manufacturing and Assembly Expectations
  • Production-intent PCB, but first revision should favor known-good integrated blocks where possible.
  • Use test points on 24V, 3.3V, GND, reset, and programming signals.
  • Ethernet and PoE layout will need controlled impedance and careful isolation/creepage review.
Firmware-Relevant Hardware Requirements
  • PWM output for dimming MOSFET gate control.
  • SPI for W5500 Ethernet controller.
  • I2C for lux sensor.
  • GPIO interrupt/input for PIR.
  • DALI transmit/receive control pins.
  • Debug/programming header.
Physical Design Expectations
  • Board size not yet specified.
  • RJ45 and rail terminal block should be board-edge accessible.
  • Keep high-voltage/high-current PoE and 24V switching areas separated from low-level logic.
Important Design Decisions
  • Use an integrated isolated PoE PD module for revision 1 instead of a discrete PoE PD controller plus custom flyback.
  • Size the production-intent 24V rail for 2–3A headroom, not only the measured 0.95A load.
  • Replace the current Ag5324 power module before layout. Use AG59824-LPB or equivalent for true 3A headroom; use Ag5810 only for a deliberate 2.5A/60W cap.
  • Use Ethernet-only architecture; no WiFi/BLE antenna.
  • Prefer W5500 + separate STM32-class MCU for production supportability.
  • Relay replaced by MOSFET to support PWM dimming.
  • Add reverse-polarity/output protection for field wiring mistakes.
  • Rev 1 DALI scope: protected DALI terminals only; full DALI PHY/transceiver and firmware commissioning are deferred to rev 2.
  • Rev 1 output abuse scope: protect against reversed passive load wiring only; externally powered reverse polarity, cable shorts, hot-plug capacitance, and inductive kick remain production/rev-2 protection requirements.
  • Layout may not proceed until AG59824-LPB has a correct reusable footprint/STEP association.
Assumptions
  • The 24V load is currently about 22.90W / 0.95A based on measured data.
  • The design target is now 2–3A lighting-output headroom; exact PoE module footprint and thermal design must be confirmed before layout.
  • 3.3V control current is provisionally 500mA peak.
  • DALI bus details are provisional until rail wiring and compliance requirements are finalized.
  • This is not yet a certified safety/compliance design.
Change Notes
  • Initial project specification created from the pasted architecture on 2026-07-04.
  • Updated with measured 22.90W load, 2–3A growth-headroom note, W5500 + STM32 direction, and reverse-polarity protection requirement.
  • Updated after follow-up module research: AG59824-LPB is the leading true-3A production candidate; Ag5810 remains a 60W/2.5A fallback. Both require library part creation/import and footprint verification before layout.
  • Implemented AG59824-LPB in the schematic as PS1, added AG59824 output/input capacitors, upgraded the 24V output PTC to 3A hold, and wired DALI terminal TVS protection. Remaining production caveats: replace provisional DF01S PoE input bridges with MOSFET rectification or higher-current bridges, verify Schottky output reverse-protection thermals at 3A, and verify exact AG59824-LPB footprint before PCB layout release.

  • Prototype / Market Context Update — 2026-07-04

  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions

  • Change Notes