DAC Design with PCM1795 and STM32
Thought for 35 sec
I found the previous connector-only blocks. I’m removing those and replacing them with actual ICs and analog-stage components now.
Worked for 10 mins 1 sec
Rebuilt the project as a real IC-level schematic instead of connector blocks: PCM1795, 3× OPA1612, LT3042 3.3 V/5 V rails, I/V feedback networks, differential output stage, RCA outputs, and power/input headers are now present and wired. ERC checks are currently clean for the checks run, and the project spec was updated.
Open items:
- The PCB layout is not done yet; per workflow, this is the schematic checkpoint before layout.
- The PCM1795 library symbol/footprint must be visually checked against the TI datasheet pinout before fabrication.
- STM32F407 exact I2S/SPI GPIO mapping is still your next firmware/pinout decision.
Suggested next steps:
- Review the schematic view and confirm it now looks like the detailed circuit you expected.
- I can next create the physical PCB placement with DAC + OPA stages tightly clustered.
- After placement approval, I can route the board with low-noise analog layout rules.
Proceed to placement
Verify PCM1795 symbol
Explain schematic
Layout best practices
Run deeper review
Refine this doc
Ask about this doc
Board Bring-Up Plan — STM32F407 PCM1795 DAC Interconnect
Prerequisites
- Equipment: multimeter, oscilloscope, current-limited bench supplies, ST-LINK/programmer, audio analyzer or powered monitor/amplifier with volume initially low.
- Firmware: see Firmware Starter file.
- Safety: do not connect op-amp supply rails until the exact OPA1612 board pinout and maximum rail voltage are confirmed.
- Prototype-specific note: the DAC is on a TSSOP56/SSOP adapter and the OPA1612 modules are on perfboard, so every adapter/module pin must be continuity-checked before first power.
- OPA rail supply: user has an LT3045/LT3094 low-noise positive/negative regulator module for ±12 V.
1. Visual Inspection
- Verify PCM1795 adapter pin-1 orientation and inspect SSOP solder joints under magnification.
- Verify each OPA1612 module pin-1 orientation and inspect solder joints/bridges.
- Verify RF/CF I/V feedback components are physically close to OPA inverting input/output pins.
- Verify no perfboard pad bridges exist between adjacent DAC/OPA signals.
- Verify J1 STM32F407 board connector orientation.
- Verify J2 PCM1795 DAC board connector orientation.
- Verify J3/J4/J5 OPA1612 board connector orientation.
- Verify J6 power connector polarity before applying power.
- Verify J7 line output wiring before connecting external audio equipment.
2. Regulator Module Pre-Test — LT3045/LT3094 ±12 V
Table
| Check | Expected result |
|---|---|
| Raw input polarity | Positive input to LT3045 side, negative input to LT3094 side, shared 0 V reference correct |
| Raw input level | About ±14 V to ±16 V DC preferred for ±12 V output; avoid excessive headroom/heat |
| No-load output | +12.0 V and −12.0 V relative to regulator 0 V |
| Loaded output | Stable +12/−12 V under a dummy load before connecting OPA modules |
| Heat | Module warm is acceptable; too hot to touch means reduce input voltage or load |
| Noise/ripple | Check with short oscilloscope ground spring; long probe ground leads can show false noise |
Important: LT3045/LT3094 ICs are 500 mA-class regulators unless the module actually parallels devices. Do not rely on the AliExpress “2 A” claim without verifying module topology and heatsinking.
3. Power Rail Verification
Table
| Rail | Source | Expected Voltage | Measure At | Current Limit | Pass Criteria |
|---|---|---|---|---|---|
| 3V3_LOGIC / DVDD | LT3042 / J6 Pin_1 | 3.3 V | PCM1795 pin 9 VDD / J1 Pin_11 / J2 Pin_11 | 200 mA initial | 3.14–3.47 V, no overheating |
| 5V_DAC_A / AVDD | LT3042 / J6 Pin_3 | 5.0 V | PCM1795 pins 15/23/28 | Board dependent | 4.85–5.15 V initial target |
| VOP_POS | LT3045/LT3094 module / J6 Pin_5 | +12 V | OPA1612 V+ pins | Current-limited | Correct polarity, no overheating |
| VOP_NEG | LT3045/LT3094 module / J6 Pin_6 | −12 V | OPA1612 V− pins | Current-limited | Correct polarity, no overheating |
| GND | J6 Pin_8 | 0 V | PCM1795 pin 8 / J1/J7 GND pins | — | Common reference present |
| AGND | J6 Pin_4 | 0 V analog ref | PCM1795 pins 16/19/24/27 and OPA analog ground node | — | Low resistance to intended analog ground |
4. PCM1795 Critical Pin Verification
Table
| Function | PCM1795 Pin | Expected |
|---|---|---|
| LRCK | 4 | Word clock present during playback |
| DATA | 5 | PCM serial data transitions |
| BCK | 6 | Bit clock present during playback |
| SCK | 7 | System clock present and synchronized with LRCK |
| DGND | 8 | 0 V digital reference |
| VDD | 9 | 3.3 V digital supply |
| MS / CS | 10 | SPI chip select, active low |
| MDI | 11 | SPI data into DAC |
| MC | 12 | SPI clock |
| MDO | 13 | Optional readback |
| RST | 14 | Active-low reset; deasserted for operation |
| VCC2R / VCC1 / VCC2L | 15 / 23 / 28 | 5 V analog supply; all within ±0.1 V of each other |
| IOUTR+ / IOUTR− | 17 / 18 | Right current outputs to I/V stage |
| IOUTL+ / IOUTL− | 25 / 26 | Left current outputs to I/V stage |
| AGND pins | 16 / 19 / 24 / 27 | Analog ground; within ±0.1 V of DGND |
5. Analog Stage Verification
Table
| Stage | Components | Expected check |
|---|---|---|
| Left I/V + | IOUTL+ → U1A | RF = 680 Ω, CF = 47–100 pF, output VL+ |
| Left I/V − | IOUTL− → U1B | RF = 680 Ω, CF = 47–100 pF, output VL− |
| Right I/V + | IOUTR+ → U2A | RF = 680 Ω, CF = 47–100 pF, output VR+ |
| Right I/V − | IOUTR− → U2B | RF = 680 Ω, CF = 47–100 pF, output VR− |
| Left diff/output | VL+/VL− → U3A | 10 kΩ 0.1% matched network, 220 pF HF cap, 100 Ω output |
| Right diff/output | VR+/VR− → U3B | 10 kΩ 0.1% matched network, 220 pF HF cap, 100 Ω output |
6. Connector and Interface Tests
- Continuity-check every named net from J1 to J2 before powering the DAC.
- Continuity-check DAC analog outputs to the correct OPA I/V inverting inputs.
- Confirm J3/J4/J5 actual OPA module pinout before connecting analog supply rails.
- Confirm J7 Pin 1 = LINE_OUT_L, Pin 2 = LINE_OUT_R, Pins 3/4 = GND.
7. Programming and Debug Interface
- Program the STM32F407 board separately using its onboard ST-LINK/SWD connector.
- Flash firmware that outputs a known low-level sine wave or silence first.
- Verify I2S clocks before connecting analog output equipment.
8. Functional Validation
Table
| Test | Input | Expected Output | Pass Criteria |
|---|---|---|---|
| Digital audio clocks | Firmware streaming silence | LRCK/BCK/SCK present | Stable clocks, correct sample rate |
| DAC init | Firmware reset + SPI/control | RST deasserted, control writes accepted | No control errors |
| One I/V stage | Known DAC tone | VL+ or selected phase | Stable waveform, no oscillation |
| Full I/V | Known DAC tone | VL+/VL−/VR+/VR− | Balanced phase outputs |
| Diff/output | Low-amplitude sine | LINE_OUT_L/R | Clean output, no clipping/oscillation |
| Mute behavior | Register MUTE or external mute | Outputs muted | Audible output drops without large pop |
Prototype Bring-Up Order
- Check all IC/module orientations and continuity first; do not trust perfboard visual routing alone.
- Bench-test LT3045/LT3094 module alone at ±12 V with dummy loads.
- Verify +3.3 V, +5 V, +12 V, −12 V rails with current limits.
- Power OPA modules alone and measure output DC/oscillation.
- Power PCM1795 digital/analog rails and verify current draw.
- Bring up STM32 → PCM1795 clocks/control while DAC outputs remain disconnected or muted.
- Build/connect one I/V channel first and verify waveform.
- Add remaining I/V channels.
- Add U3 differential/output stage and RCA output last.
Open Bring-Up Items
- Exact STM32F407 board/header pin mapping is TBD.
- Linear supply current limits/earth reference are TBD.
- Confirm whether the LT3045/LT3094 module has genuine LT/ADI parts and whether multiple regulator ICs are paralleled for higher current.
Prerequisites
1. Visual Inspection
2. Regulator Module Pre-Test — LT3045/LT3094 ±12 V
3. Power Rail Verification
4. PCM1795 Critical Pin Verification
5. Analog Stage Verification
6. Connector and Interface Tests
7. Programming and Debug Interface
8. Functional Validation
Prototype Bring-Up Order
Open Bring-Up Items
