DAC Design with PCM1795 and STM32

V

valentin-manol

yes please

flux

I’ll rebuild this as a real IC-level DAC schematic: PCM1795 pins, three OPA1612 dual op-amps, I/V parts, differential outputs, regulators/connectors, then verify ERC before stopping at the schematic stage.

flux

I found the previous connector-only blocks. I’m removing those and replacing them with actual ICs and analog-stage components now.

flux

Rebuilt the project as a real IC-level schematic instead of connector blocks: PCM1795, 3× OPA1612, LT3042 3.3 V/5 V rails, I/V feedback networks, differential output stage, RCA outputs, and power/input headers are now present and wired. ERC checks are currently clean for the checks run, and the project spec was updated.
Open items:
  • The PCB layout is not done yet; per workflow, this is the schematic checkpoint before layout.
  • The PCM1795 library symbol/footprint must be visually checked against the TI datasheet pinout before fabrication.
  • STM32F407 exact I2S/SPI GPIO mapping is still your next firmware/pinout decision.
Suggested next steps:
  1. Review the schematic view and confirm it now looks like the detailed circuit you expected.
  2. I can next create the physical PCB placement with DAC + OPA stages tightly clustered.
  3. After placement approval, I can route the board with low-noise analog layout rules.
Proceed to placement
Verify PCM1795 symbol
Explain schematic
Layout best practices
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Schematic

Layout

3D View

PCM1795 + OPA1612 DAC Card Schematic Extraction
Source
  • Uploaded file: pcm1795_opa1612_dac_card_schematic.pdf
  • Uploaded datasheet: pcm1795.pdf
  • Note: Verify physical adapter orientation and continuity before soldering.
PCM1795 Pinout — 28-Pin SSOP DB Package

Table

PinNameFunction
1ZEROLLeft zero flag
2ZERORRight zero flag
3MSELI2C/SPI select; active-low SPI select
4LRCKLeft/right word clock input
5DATASerial audio data input
6BCKBit clock input
7SCKSystem clock input
8DGNDDigital ground
9VDD3.3 V digital supply
10MSMode-control chip select, active low
11MDIMode-control data input
12MCMode-control clock input
13MDOMode-control readback output / I2C open-drain output
14RSTReset, active low
15VCC2R5 V analog supply, right DACFF
16AGND3RRight DACFF analog ground
17IOUTR+Right analog current output +
18IOUTR−Right analog current output −
19AGND1Analog ground, internal bias
20IREFOutput current reference bias pin
21VCOMRRight internal bias decoupling pin
22VCOMLLeft internal bias decoupling pin
23VCC15 V analog supply
24AGND2Analog ground, internal bias
25IOUTL+Left analog current output +
26IOUTL−Left analog current output −
27AGND3LLeft DACFF analog ground
28VCC2L5 V analog supply, left DACFF
PCM1795 Operating Requirements

Table

ItemRequirement
Digital supplyVDD = 3.0–3.6 V, nominal 3.3 V
Analog suppliesVCC1/VCC2L/VCC2R = 4.75–5.25 V, nominal 5 V
Supply matchingVCC1/VCC2L/VCC2R difference must stay within ±0.1 V
Ground matchingAGND/DGND differences must stay within ±0.1 V
Digital inputs5 V tolerant Schmitt-trigger inputs; VIH ≥ 2.0 V, VIL ≤ 0.8 V
PCM formatsStandard, I2S, left-justified; default is 32-bit I2S
Sample rate10–200 kHz PCM
System clock128/192/256/384/512/768 × fS
Current outputAbout 4 mA p-p per output pin at 0 dBFS
Architecture
  • PCM1795 current-output stereo DAC.
  • Three OPA1612 dual op-amps total:
    • U1: left-channel I/V conversion for IOUTL+ and IOUTL−.
    • U2: right-channel I/V conversion for IOUTR+ and IOUTR−.
    • U3: differential-to-single-ended output / low-pass filter / buffer for left and right RCA outputs.
  • STM32F407 provides I2S audio: BCK, LRCK/WS, DATA, SCK/MCLK.
Digital Input Recommendations

Table

SignalPCM1795 PinSourceRecommended part
LRCK/WS4STM32F40722–47 Ω series resistor near STM32
DATA5STM32F40722–47 Ω series resistor near STM32
BCK6STM32F40722–47 Ω series resistor near STM32
SCK / system clock7STM32F407 or low-jitter oscillatorStart around 10–47 Ω series resistor near source
MS / CS10STM32F407 SPI CSActive low
MDI / MOSI11STM32F407 SPI MOSIMode-control data
MC / SCK12STM32F407 SPI SCKMode-control clock
MDO / MISO13STM32F407 SPI MISO optionalReadback
RST14STM32F407 GPIOActive low reset
MSEL3Strap/controlLow selects SPI
PCM1795 Supplies / Decoupling

Table

RailPinsSourceLocal capacitorsNotes
VDD digital9LT3042 3.3 V100 nF X7R + 10 µFShort return to DGND
VCC analog15, 23, 28LT3042 5 V100 nF X7R per supply pin + 10 µF + 47 µFShort return to AGND
VCOM21, 22Internal bias pinsDecouple close per datasheet layoutKeep away from digital routing
IREF20Current reference biasFollow datasheet/reference circuitSensitive analog node
I/V Conversion Starting Values
Each PCM1795 current-output pin is converted by an OPA1612 inverting I/V stage.

Table

ChannelDAC outputPCM1795 PinOPA stageFeedbackCompensationNon-inverting bias
Left +IOUTL+25U1A680 Ω 0.1%47–100 pF C0G/NP0 parallel with RF680 Ω to AGND
Left −IOUTL−26U1B680 Ω 0.1%47–100 pF C0G/NP0 parallel with RF680 Ω to AGND
Right +IOUTR+17U2A680 Ω 0.1%47–100 pF C0G/NP0 parallel with RF680 Ω to AGND
Right −IOUTR−18U2B680 Ω 0.1%47–100 pF C0G/NP0 parallel with RF680 Ω to AGND
Expected output scale: PCM1795 current output is about 4 mA p-p at 0 dBFS, so 680 Ω gives about 2.72 Vpp per phase and about 5.44 Vpp differential before output-stage losses. Tune RF to 390 Ω if too hot or 1 kΩ if too low.
Differential Output Stage
U3 is a unity-gain differential amplifier / filter stage.

Table

ChannelInputsResistor networkFilter / output parts
LeftVL+, VL−10 kΩ 0.1% matched network220 pF feedback HF filter, 100 Ω output resistor, optional 2.2 nF output RF shunt
RightVR+, VR−10 kΩ 0.1% matched network220 pF feedback HF filter, 100 Ω output resistor, optional 2.2 nF output RF shunt
If output phase is inverted, swap VL+/VL− or VR+/VR− at the differential stage, keeping both channels consistent.
OPA1612 Power / Decoupling
  • OPA rails: +12 V / −12 V.
  • User regulator module: LT3045/LT3094 positive/negative low-noise module is suitable if validated.
  • Each OPA1612 package: 100 nF per rail + 10 µF local reservoir at the package.
  • Analog rail bulk near power entry: 100–220 µF per rail.
Grounding / Layout Critical Points
  • TI recommends the same ground between AGND and DGND to avoid voltage differences, but digital return currents must avoid AGND pins and I/V input nodes.
  • Use star-ish routing: DAC analog ground, OPA ground, and regulator returns meet at the DAC card ground reference area.
  • Route PCM1795 current outputs as extremely short traces/wires directly to OPA inverting inputs.
  • Keep BCK/LRCK/DATA/SCK and control lines away from I/V summing nodes.
  • Use top-layer/local ground shielding around PCM1795 where practical and tie to the main ground reference with multiple low-impedance connections.
Bring-Up Order From PDF + Datasheet
  1. Power rails only: verify +5 V, +3.3 V, +12 V, −12 V with current limits.
  2. Power PCM1795: verify no overheating and correct current draw.
  3. Scope LRCK, DATA, BCK, and SCK at DAC pins before enabling analog output stage.
  4. Build one channel I/V first; verify sine/triangle waveform on scope before adding second channel.
  5. Add U3 differential stage and RCA output after I/V outputs are correct.
BOM Values Extracted

Table

Ref / FunctionValue / PartQtyNotes
DACPCM17951Current-output stereo DAC
Op-ampsOPA16123Six op-amp channels total
I/V feedback680 Ω 0.1%4Also buy 390 Ω and 1 kΩ for tuning
I/V compensation47–100 pF C0G/NP04Parallel with RF
I/V bias680 Ω 1%4Non-inverting input to AGND; may be 0 Ω after testing
Differential amp resistors10 kΩ 0.1%8Matched network
Differential feedback caps220 pF C0G/NP02–4Matched if used in both arms
Output isolation100 Ω 1%2Before RCA output
Output RF shunt2.2 nF film/C0G2Optional
I2S damping22–47 Ω3–4BCK, LRCK, DATA, optional MCLK/SCK
Decoupling100 nF X7R20+At IC supply pins/rail groups
Local reservoir10 µF10+Local rail reservoir
Bulk47/100/220 µFas neededNear card power entry

  • Source

  • PCM1795 Pinout — 28-Pin SSOP DB Package

  • PCM1795 Operating Requirements

  • Architecture

  • Digital Input Recommendations

  • PCM1795 Supplies / Decoupling

  • I/V Conversion Starting Values

  • Differential Output Stage

  • OPA1612 Power / Decoupling

  • Grounding / Layout Critical Points

  • Bring-Up Order From PDF + Datasheet

  • BOM Values Extracted