DAC Design with PCM1795 and STM32
Thought for 35 sec
I found the previous connector-only blocks. I’m removing those and replacing them with actual ICs and analog-stage components now.
Worked for 10 mins 1 sec
Rebuilt the project as a real IC-level schematic instead of connector blocks: PCM1795, 3× OPA1612, LT3042 3.3 V/5 V rails, I/V feedback networks, differential output stage, RCA outputs, and power/input headers are now present and wired. ERC checks are currently clean for the checks run, and the project spec was updated.
Open items:
- The PCB layout is not done yet; per workflow, this is the schematic checkpoint before layout.
- The PCM1795 library symbol/footprint must be visually checked against the TI datasheet pinout before fabrication.
- STM32F407 exact I2S/SPI GPIO mapping is still your next firmware/pinout decision.
Suggested next steps:
- Review the schematic view and confirm it now looks like the detailed circuit you expected.
- I can next create the physical PCB placement with DAC + OPA stages tightly clustered.
- After placement approval, I can route the board with low-noise analog layout rules.
Proceed to placement
Verify PCM1795 symbol
Explain schematic
Layout best practices
Run deeper review
Refine this doc
Ask about this doc
PCM1795 + OPA1612 DAC Card Schematic Extraction
Source
- Uploaded file:
pcm1795_opa1612_dac_card_schematic.pdf - Uploaded datasheet:
pcm1795.pdf - Note: Verify physical adapter orientation and continuity before soldering.
PCM1795 Pinout — 28-Pin SSOP DB Package
Table
| Pin | Name | Function |
|---|---|---|
| 1 | ZEROL | Left zero flag |
| 2 | ZEROR | Right zero flag |
| 3 | MSEL | I2C/SPI select; active-low SPI select |
| 4 | LRCK | Left/right word clock input |
| 5 | DATA | Serial audio data input |
| 6 | BCK | Bit clock input |
| 7 | SCK | System clock input |
| 8 | DGND | Digital ground |
| 9 | VDD | 3.3 V digital supply |
| 10 | MS | Mode-control chip select, active low |
| 11 | MDI | Mode-control data input |
| 12 | MC | Mode-control clock input |
| 13 | MDO | Mode-control readback output / I2C open-drain output |
| 14 | RST | Reset, active low |
| 15 | VCC2R | 5 V analog supply, right DACFF |
| 16 | AGND3R | Right DACFF analog ground |
| 17 | IOUTR+ | Right analog current output + |
| 18 | IOUTR− | Right analog current output − |
| 19 | AGND1 | Analog ground, internal bias |
| 20 | IREF | Output current reference bias pin |
| 21 | VCOMR | Right internal bias decoupling pin |
| 22 | VCOML | Left internal bias decoupling pin |
| 23 | VCC1 | 5 V analog supply |
| 24 | AGND2 | Analog ground, internal bias |
| 25 | IOUTL+ | Left analog current output + |
| 26 | IOUTL− | Left analog current output − |
| 27 | AGND3L | Left DACFF analog ground |
| 28 | VCC2L | 5 V analog supply, left DACFF |
PCM1795 Operating Requirements
Table
| Item | Requirement |
|---|---|
| Digital supply | VDD = 3.0–3.6 V, nominal 3.3 V |
| Analog supplies | VCC1/VCC2L/VCC2R = 4.75–5.25 V, nominal 5 V |
| Supply matching | VCC1/VCC2L/VCC2R difference must stay within ±0.1 V |
| Ground matching | AGND/DGND differences must stay within ±0.1 V |
| Digital inputs | 5 V tolerant Schmitt-trigger inputs; VIH ≥ 2.0 V, VIL ≤ 0.8 V |
| PCM formats | Standard, I2S, left-justified; default is 32-bit I2S |
| Sample rate | 10–200 kHz PCM |
| System clock | 128/192/256/384/512/768 × fS |
| Current output | About 4 mA p-p per output pin at 0 dBFS |
Architecture
- PCM1795 current-output stereo DAC.
- Three OPA1612 dual op-amps total:
- U1: left-channel I/V conversion for IOUTL+ and IOUTL−.
- U2: right-channel I/V conversion for IOUTR+ and IOUTR−.
- U3: differential-to-single-ended output / low-pass filter / buffer for left and right RCA outputs.
- STM32F407 provides I2S audio: BCK, LRCK/WS, DATA, SCK/MCLK.
Digital Input Recommendations
Table
| Signal | PCM1795 Pin | Source | Recommended part |
|---|---|---|---|
| LRCK/WS | 4 | STM32F407 | 22–47 Ω series resistor near STM32 |
| DATA | 5 | STM32F407 | 22–47 Ω series resistor near STM32 |
| BCK | 6 | STM32F407 | 22–47 Ω series resistor near STM32 |
| SCK / system clock | 7 | STM32F407 or low-jitter oscillator | Start around 10–47 Ω series resistor near source |
| MS / CS | 10 | STM32F407 SPI CS | Active low |
| MDI / MOSI | 11 | STM32F407 SPI MOSI | Mode-control data |
| MC / SCK | 12 | STM32F407 SPI SCK | Mode-control clock |
| MDO / MISO | 13 | STM32F407 SPI MISO optional | Readback |
| RST | 14 | STM32F407 GPIO | Active low reset |
| MSEL | 3 | Strap/control | Low selects SPI |
PCM1795 Supplies / Decoupling
Table
| Rail | Pins | Source | Local capacitors | Notes |
|---|---|---|---|---|
| VDD digital | 9 | LT3042 3.3 V | 100 nF X7R + 10 µF | Short return to DGND |
| VCC analog | 15, 23, 28 | LT3042 5 V | 100 nF X7R per supply pin + 10 µF + 47 µF | Short return to AGND |
| VCOM | 21, 22 | Internal bias pins | Decouple close per datasheet layout | Keep away from digital routing |
| IREF | 20 | Current reference bias | Follow datasheet/reference circuit | Sensitive analog node |
I/V Conversion Starting Values
Each PCM1795 current-output pin is converted by an OPA1612 inverting I/V stage.
Table
| Channel | DAC output | PCM1795 Pin | OPA stage | Feedback | Compensation | Non-inverting bias |
|---|---|---|---|---|---|---|
| Left + | IOUTL+ | 25 | U1A | 680 Ω 0.1% | 47–100 pF C0G/NP0 parallel with RF | 680 Ω to AGND |
| Left − | IOUTL− | 26 | U1B | 680 Ω 0.1% | 47–100 pF C0G/NP0 parallel with RF | 680 Ω to AGND |
| Right + | IOUTR+ | 17 | U2A | 680 Ω 0.1% | 47–100 pF C0G/NP0 parallel with RF | 680 Ω to AGND |
| Right − | IOUTR− | 18 | U2B | 680 Ω 0.1% | 47–100 pF C0G/NP0 parallel with RF | 680 Ω to AGND |
Expected output scale: PCM1795 current output is about 4 mA p-p at 0 dBFS, so 680 Ω gives about 2.72 Vpp per phase and about 5.44 Vpp differential before output-stage losses. Tune RF to 390 Ω if too hot or 1 kΩ if too low.
Differential Output Stage
U3 is a unity-gain differential amplifier / filter stage.
Table
| Channel | Inputs | Resistor network | Filter / output parts |
|---|---|---|---|
| Left | VL+, VL− | 10 kΩ 0.1% matched network | 220 pF feedback HF filter, 100 Ω output resistor, optional 2.2 nF output RF shunt |
| Right | VR+, VR− | 10 kΩ 0.1% matched network | 220 pF feedback HF filter, 100 Ω output resistor, optional 2.2 nF output RF shunt |
If output phase is inverted, swap VL+/VL− or VR+/VR− at the differential stage, keeping both channels consistent.
OPA1612 Power / Decoupling
- OPA rails: +12 V / −12 V.
- User regulator module: LT3045/LT3094 positive/negative low-noise module is suitable if validated.
- Each OPA1612 package: 100 nF per rail + 10 µF local reservoir at the package.
- Analog rail bulk near power entry: 100–220 µF per rail.
Grounding / Layout Critical Points
- TI recommends the same ground between AGND and DGND to avoid voltage differences, but digital return currents must avoid AGND pins and I/V input nodes.
- Use star-ish routing: DAC analog ground, OPA ground, and regulator returns meet at the DAC card ground reference area.
- Route PCM1795 current outputs as extremely short traces/wires directly to OPA inverting inputs.
- Keep BCK/LRCK/DATA/SCK and control lines away from I/V summing nodes.
- Use top-layer/local ground shielding around PCM1795 where practical and tie to the main ground reference with multiple low-impedance connections.
Bring-Up Order From PDF + Datasheet
- Power rails only: verify +5 V, +3.3 V, +12 V, −12 V with current limits.
- Power PCM1795: verify no overheating and correct current draw.
- Scope LRCK, DATA, BCK, and SCK at DAC pins before enabling analog output stage.
- Build one channel I/V first; verify sine/triangle waveform on scope before adding second channel.
- Add U3 differential stage and RCA output after I/V outputs are correct.
BOM Values Extracted
Table
| Ref / Function | Value / Part | Qty | Notes |
|---|---|---|---|
| DAC | PCM1795 | 1 | Current-output stereo DAC |
| Op-amps | OPA1612 | 3 | Six op-amp channels total |
| I/V feedback | 680 Ω 0.1% | 4 | Also buy 390 Ω and 1 kΩ for tuning |
| I/V compensation | 47–100 pF C0G/NP0 | 4 | Parallel with RF |
| I/V bias | 680 Ω 1% | 4 | Non-inverting input to AGND; may be 0 Ω after testing |
| Differential amp resistors | 10 kΩ 0.1% | 8 | Matched network |
| Differential feedback caps | 220 pF C0G/NP0 | 2–4 | Matched if used in both arms |
| Output isolation | 100 Ω 1% | 2 | Before RCA output |
| Output RF shunt | 2.2 nF film/C0G | 2 | Optional |
| I2S damping | 22–47 Ω | 3–4 | BCK, LRCK, DATA, optional MCLK/SCK |
| Decoupling | 100 nF X7R | 20+ | At IC supply pins/rail groups |
| Local reservoir | 10 µF | 10+ | Local rail reservoir |
| Bulk | 47/100/220 µF | as needed | Near card power entry |
Source
PCM1795 Pinout — 28-Pin SSOP DB Package
PCM1795 Operating Requirements
Architecture
Digital Input Recommendations
PCM1795 Supplies / Decoupling
I/V Conversion Starting Values
Differential Output Stage
OPA1612 Power / Decoupling
Grounding / Layout Critical Points
Bring-Up Order From PDF + Datasheet
BOM Values Extracted
